Designing of Different Types of Multipliers

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DESIGN AND IMPLEMENTATION OF DIFFERENT MULTIPLIERS USING VHDL A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Bachelor of Technology in Electronics and Communication Engineering By MOUMITA GHOSH

Department of Electronics and Communication Engineering National Institute of Technology Rourkela 2007

National Institute of Technology Rourkela

CERTIFICATE

This is to certify that the thesis entitled, “DESIGN AND IMPLEMENTATION OF DIFFERENT MULTIPLIERS USING VHDL ” submitted by Ms Moumita Ghosh in partial fulfillments for the requirements for the award of Bachelor of Technology Degree in Electronics and Communication Engineering at National Institute of Technology, Rourkela (Deemed University) is an authentic work carried out by her under my supervision and guidance.

To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other University / Institute for the award of any Degree or Diploma.

Date:

Prof. Dr. K.K Mahapatra Dept. of Electronics and Communication Engineering National Institute of Technology Rourkela - 769008

ACKNOWLEDGEMENT

I would like to articulate my profound gratitude and indebtedness to my project guide Prof.Dr. K.K Mahapatra who has always been a constant motivation and guiding factor throughout the project time in and out as well. It has been a great pleasure for me to get a opportunity to work under him and complete the project successfully.

I wish to extend my sincere thanks to Prof.Dr. G Panda, Head of our Department, for approving our project work with great interest. I would also like to mention Mr. Jitendra Behera, Ms Durga Digdarshani and Mr Sushant Pattnaik assistance. M.Tech Student, for their cooperation and constantly rendered

It is my pleasure to refer VHDL, Acrobat Reader and Microsoft Word exclusive of which the whole process, right from simulation to compilation of this report would have been impossible.

An undertaking of this nature could never have been attempted with our reference to and inspiration from the works of others whose details are mentioned in references section. I acknowledge my indebtedness to all of them. Last but not the least, my sincere thanks to all of my friends who have patiently extended all sorts of help for accomplishing this undertaking.

CONTENTS

Abstract……………………………………………………………………………… 05

List of Figures………………………………………………………………………………ii List of Tables………………………………………………………………………………… iii

Introduction………………………….………………………………………………09 VHDL ……………………………………………………………………………....14 Filters……………………...……………………………………….…………...…...26 Type of filters…………………………………………….…..…………………......29 Adders….………………………………………………….. ………………………31 Binary multipliers…..…………….…………………………………….……..…….41 Results……………………………..…………………….…….………....................54 Conclusion………………………………………………………………………… .57 Refrences…………………………………………………………………………….59

ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this problem by comparing a few multipliers. This project presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In this project we compare the working of the three multiplier by implementing each of them separately in FIR filter.

The parallel multipliers like radix 2 and radix 4 modified booth multiplier does the computations using lesser adders and lesser iterative steps. As a result of which they occupy lessr space as compared to the serial multiplier. This a very important criteria because in the fabrication of chips and high performance system requires components...
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