Design Technique of P-Type Cmos Circuit for Gate-Leakage Reduction in Deep Submicron
Design technique of P-type CMOS circuit for gate-leakage Reduction in deep submicron
Aneesha R1, Shabnoor Naaz M2
8th Semester, E&C Dept, BIT Mangalore
1anee.star@ymail.com
2naazshaik.44@gmail.com
Abstract— Before the CMOS process is scaled into deep sub-micron process, dynamic energy loss has always dominated power dissipation, while leakage power is little. The aggressive scaling of device dimensions and threshold voltage has significantly increased leakage current exponentially, thus the MOS devices will no longer be totally turned-off anymore. The power dissipation caused by leakage current can’t be neglected anymore, which attracts extensive attentions. Based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, it is used for designing circuit for reducing gate leakage power. Series of iterative steps are carried out to find the design perspective effect in different technologies.
Keywords— ECB, Gate leakage, HVB, PDCVSL, PCPL.
* I Introduction
With the substantial growth in portable computing and wireless communication in the last few years, power dissipation has become a critical issue. Problems with heat removal and cooling are worsening because the magnitude of power dissipated per unit area is growing with scaling. Years ago, portable battery-powered applications were characterized by low computational requirement. Nowadays, these applications require the computational performance similar to as non-portable ones. It is important to extend the battery life as much as possible. For these reasons power dissipation becomes a challenge for circuit designers and a critical factor in the future of microelectronics. There are three components of power dissipation in digital CMOS Circuits, namely dynamic, short circuit and leakage power dissipation. Dynamic switching power dissipation is caused by charging capacitances in the circuit during each low-to-high output transition, by the load capacitance. The
Aneesha R1, Shabnoor Naaz M2
8th Semester, E&C Dept, BIT Mangalore
1anee.star@ymail.com
2naazshaik.44@gmail.com
Abstract— Before the CMOS process is scaled into deep sub-micron process, dynamic energy loss has always dominated power dissipation, while leakage power is little. The aggressive scaling of device dimensions and threshold voltage has significantly increased leakage current exponentially, thus the MOS devices will no longer be totally turned-off anymore. The power dissipation caused by leakage current can’t be neglected anymore, which attracts extensive attentions. Based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, it is used for designing circuit for reducing gate leakage power. Series of iterative steps are carried out to find the design perspective effect in different technologies.
Keywords— ECB, Gate leakage, HVB, PDCVSL, PCPL.
* I Introduction
With the substantial growth in portable computing and wireless communication in the last few years, power dissipation has become a critical issue. Problems with heat removal and cooling are worsening because the magnitude of power dissipated per unit area is growing with scaling. Years ago, portable battery-powered applications were characterized by low computational requirement. Nowadays, these applications require the computational performance similar to as non-portable ones. It is important to extend the battery life as much as possible. For these reasons power dissipation becomes a challenge for circuit designers and a critical factor in the future of microelectronics. There are three components of power dissipation in digital CMOS Circuits, namely dynamic, short circuit and leakage power dissipation. Dynamic switching power dissipation is caused by charging capacitances in the circuit during each low-to-high output transition, by the load capacitance. The