Design technique of P-type CMOS circuit for gate-leakage Reduction in deep submicron Aneesha R1, Shabnoor Naaz M2
8th Semester, E&C Dept, BIT Mangalore
Abstract— Before the CMOS process is scaled into deep sub-micron process, dynamic energy loss has always dominated power dissipation, while leakage power is little. The aggressive scaling of device dimensions and threshold voltage has significantly increased leakage current exponentially, thus the MOS devices will no longer be totally turned-off anymore. The power dissipation caused by leakage current can’t be neglected anymore, which attracts extensive attentions. Based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, it is used for designing circuit for reducing gate leakage power. Series of iterative steps are carried out to find the design perspective effect in different technologies.
Keywords— ECB, Gate leakage, HVB, PDCVSL, PCPL.
* I Introduction
With the substantial growth in portable computing and wireless communication in the last few years, power dissipation has become a critical issue. Problems with heat removal and cooling are worsening because the magnitude of power dissipated per unit area is growing with scaling. Years ago, portable battery-powered applications were characterized by low computational requirement. Nowadays, these applications require the computational performance similar to as non-portable ones. It is important to extend the battery life as much as possible. For these reasons power dissipation becomes a challenge for circuit designers and a critical factor in the future of microelectronics. There are three components of power dissipation in digital CMOS Circuits, namely dynamic, short circuit and leakage power dissipation. Dynamic switching power dissipation is caused by charging capacitances in the circuit during each low-to-high output transition, by the load capacitance. The dynamic switching power dissipation was the dominant factor compared with other components of power dissipation in digital CMOS circuits for technologies up to 0.18μm, where it is about 90% of total circuit dissipation. With the technology scaling, supply voltage needs to be reduce due to dynamic power and reliability issues. However, it requires the scaling of the device threshold voltage (Vth) to maintain a reasonable gate over drive . The Vth reduction, result in an exponential increase in the subthreshold current. Moreover, to control the short channel effects (SCEs) and to maintain the transistor drive strength at low supply voltage, oxide thickness needs to be also scaled down. The aggressive scaling of oxide thickness results in a high tunnelling current through the transistor gate insulator. Furthermore, scaled devices require the use of the higher substrate doping density. It causes significantly leakage current through these drain- and source-to substrate junctions under high reversed bias.
II Leakage current Mechanism
For nanometre devices, leakage current is dominated by subthreshold leakage, gate-oxide tunnelling leakage and reverse-bias pn-junction leakage. Those three major leakage current mechanisms are illustrated in fig1.
Fig1: Major leakage mechanisms in MOS transistor.
Supply voltage has been scaled down to keep dynamic power consumption under control. To maintain a high drive current capability, the threshold voltage (Vth) has to be scaled too. However, the Vth scaling results in increasing subthreshold leakage currents. Subthreshold current occurs between drain and source when transistor is operating in weak inversion region, i.e., the gate voltage is lower than the Vth. The drain-to-source current is composed by drift current and diffusion current. The drift current is the dominant mechanism in strong inversion regime, when the gate-to-source voltage exceeds the Vth. In weak inversion, the minority...
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