1Department of Electronics and Communication Engineering, KITS, Warangal firstname.lastname@example.org
2 B.Tech (ECE),KITS, Warangal
email@example.com, firstname.lastname@example.org, email@example.com
In this paper, an area efficient multiplier architecture is presented. The architecture is based on Ancient algorithms of the Vedas, propounded in the Vedic Mathematics scripture of Sri Bharati Krishna Tirthaji Maharaja. The multiplication algorithm used here is called Nikhilam Navatascaramam Dasatah. The multiplier based on the ancient technique is compared with the modern multiplier to highlight the speed and power superiority of the Vedic Multipliers.
Digital Multiplier, Nikhilam algorithm,CSA.
The multiplier is one of the fundamental hardware blocks in many Digital Signal Processing systems for performing different operations like frequency domain filtering(FIR,IIR),frequency transformations(FFT), etc., Some of the important arithmetic functions implemented by the multiplier in the DSPs are Multiply and Accumulate (MAC), inner product. Not just in the DSP systems, the digital multiplier is an indispensable block in Digital Image Processing systems, and even in Microprocessor in its ALU. The former microprocessors did not have a Multiplier block, instead of which they used multiply routines, for shifting and adding the partial results to produce the final product result. But with the enhanced levels of integration in the latest VLSI circuits day-by-day, the task of designing a multiplier block has began receiving immense devotion in the design of digital systems. The multiplier, being the most significant block in many such digital systems, their speed and efficiency are primarily dependent upon the speed, area, throughput efficiency of the multipliers implemented in these systems. The other feature of the multiplier which has to be given quantitative concern in designing of the systems is Power Dissipation, viz. the multiplier is a source of high power dissipation. Consequently, many algorithms have been suggested in different literatures aiming at improvising any one or more of the characteristics-speed, area, throughput, power of the digital multiplier. The Booth Multiplier, CSA array method, Wallace tree method, and the Booth recording multiplier are some of the important architectures proposed to improvise the digital multiplier.
In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is being proposed. The crucial aspect of this proposed architecture is that it is based on an Ancient Indian Vedic Mathematics. This paper gives information of "Nikhilam Sutra" which can increase the speed of multiplier by reducing the number of iterations. Vedic Mathematics also suggests one more formula for multiplication i.e. "Urdhva Tiryagbhyam" which is utilized for multiplication to improve the speed, area parameters of multipliers.
2. CONCEPTUAL OVERVIEW
2.1. Vedic Mathematics
Veda, by definition, is ‘knowledge’. The Vedic Math has a much ancient origin though attributed to the techniques rediscovered between 1911-1918, by Sri Bharati Krshna Tirthaji Maharaja. Vedic mathematics is the ancient system of mathematics, or, precisely, it is a distinct technique of calculations based on simple rules and principles with which any mathematical problem can be solved, whether it may be arithmetic, algebra, geometry, trigonometry or even calculus. The Vedic mathematics is a coherent collective combination of 16 Sutras(Formulae) and 16 Sub-Sutras(the corollaries of the formulae). According to a theory, “The sutras of Vedic Mathematics are the software for the cosmic computer that runs this universe.” The calibre of Vedic mathematics lies in the fact that it scales down the otherwise cumbersome-looking...