Design & Implementation of a Sequence Detector on an Fpga

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  • Topic: State diagram, Clock signal, Logic gate
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  • Published : February 7, 2013
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Design & Implementation of a Sequence Detector on an FPGA

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EE3076 – Advanced Digital Systems

28th January 2013
Revision 1.0

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Contents

Contents1
Tables and Figures3
Revision History5
1Introduction6
1.1Assignment Objectives6
1.2Assignment Description6
1.3FPGA Board7
1.4Pre – anticipated issue: Switch Bounce8
2Design9
2.1User Design Specification9
2.2High-Level Architecture9
2.3Formal Design Specification10
2.3.1Clock Divider10
2.3.2Keypad Driver11
2.3.3Sequence Detector Design12
2.3.4LED Driver14
3Implementation15
3.1Clock Divider15
3.1.1Port and Entity Declarations15
3.1.2Counter Implemented Clock Divider16
3.2Keypad Driver16
3.2.1Port and Entity Declaration16
3.2.2Keypad Button Translation17
3.2.3‘Key Held Down’ Filter17
3.2.4Switch Bounce & Output P Filter18
3.3Sequence Detector19
3.3.1Port and Entity Declaration19
3.3.2Clock Enable Logic19
3.3.3Reset Logic and Symbol Counter Driving Logic19
3.3.4Next State Logic20
3.3.5Output Logic21
3.4Led Driver21
3.4.1Port and Entity Declaration21
3.4.2Led Driving Logic, Pattern Generation and Reset22
4Testing & Verification23
4.1Clock Divider23
4.2Keypad Driver23
4.3Sequence Detector25
4.3.1Initial Reset25
4.3.2State Transitions for Correct Sequence25
4.3.3Reset After Correct Sequence Detected26
4.3.4State Transition for Incorrect Sequence27
4.3.5Output after 25 Symbols Entered27
4.4Led Driver28
4.5Top-Level Testing29
5Conclusion30

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Tables and Figures

Figure 1:FPGA Board Spartan 6 Family6
Figure 2: Switch Bounce Phenomena Observed On Oscilloscope7
Figure 3: High-level Architecture8
Figure 4: Clock Divider Flowchart9
Figure 5: Keypad Driver Table10
Figure 6: Keypad Driver Flowchart10
Figure 7: FSM – Sequence Detector12
Figure 8: Moore FSM Architecture12
Figure 9: Graphical Representation of Top-Level Module14
Figure 10: Clock Divider Block Implementation14
Figure 11: Clock Divider Port Declarations15
Figure 12: Counter Implemented Clock Divider15
Figure 13: Keypad Driver Block Implementation15
Figure 14: Keypad Driver Port Declarations16
Figure 15: Keypad Button Translation Implementation16
Figure 16: Button Release Mechanism Implementation16
Figure 17: Additional Counter & Output P Filter Implementation17
Figure 18: Sequence Detector Block Implementation18
Figure 19: Sequence Detector Port Declarations18
Figure 20: Sequence Detector Clock Enable Logic18
Figure 21: Sequence Detector Reset & Symbol Counter Logic19
Figure 22: Current State Signal Declaration19
Figure 23: Current State Signal Declaration19
Figure 24: State Machine Output Logic Implementation20
Figure 25: Led Driver Block Implementation20
Figure 26: Led Driver Port Declarations20
Figure 27: Led Driving Logic, Pattern Generation and Reset Implementation21
Figure 28: ‘clk_out_led’ Verified as 338ms Period – Simulation22
Figure 29: ‘clk_out_21_ms’ Verified as 21ms Period – Simulation22
Figure 30: Keypad Driver at Idle – Simulation22
Figure 31: Keypad driver – Key 1 Translation – Simulation23
Figure 32: Keypad driver – Key 2 Translation – Simulation23
Figure 33: Keypad driver – Key 3 Translation – Simulation23
Figure 34: Keypad driver – Key 4 Translation – Simulation23
Figure 35: Sequence Detector – Inital Reset – Simulation24
Figure 36: Sequence Detector – State A to State B - Simulation24
Figure 37: Sequence Detector – State B to State C - Simulation25...
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