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Reg. No. :

Question Paper Code :

66167
B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.

2

Sixth Semester

Computer Science and Engineering

11

CS 2354 — ADVANCED COMPUTER ARCHITECTURE
(Regulation 2008)
Time : Three hours

Maximum : 100 marks

Answer ALL questions.

2

PART A — (10 × 2 = 20 marks)
What is instruction level parallelism?

2.

What are the advantages of loop unrolling?

3.

What are the limitations of VLIW?

4.

What is the use of branch-target buffer?

5.

Distinguish between shared memory multiprocessor and message-passing multiprocessor.

6.

Differentiate multithreading computers from multiprocessor systems

7.

Define the terms cache miss and cache hit.

9.
10.

2

11

8.

11

1.

What is RAID?

What is a multi-core processor?
What is a cell processor?

PART B — (5 × 16 = 80 marks)
11.

(a)

(i)
Explain the data and name dependencies with suitable
example.
(10)
(ii)

Discuss about the benefits and limitations of static branch
prediction and dynamic branch prediction
(6)

12.

(a)

Briefly explain how to overcome data hazards with dynamic
scheduling using Tomasula’s approach.

11

(b)

2

Or

(i)

Describe the architecture of Itanium processor with the help of a block diagram.
(8)

(ii)

Explain how ILP is achieved in EPIC processors

(16)

(8)

Or

(i)

Briefly compare instruction level parallelism with thread-level parallelism.
(8)
Explain the basic architecture of a distributed memory
multiprocessor system.

2

What are the advantages and disadvantages of software-based
and hardware-based speculation mechanism?
(8)

(ii)

(a)

Describe the architectural features of IA64 processor in detail.(8)

(ii)

13.

(i)

11

(b)

(8)

Or
(i)

(a)

(b)

(10)

What is multithreading and what are the advantages of
multithreading?
(6)

11

(ii)

14.

Explain various memory consistency models in detail.

2

(b)

What is meant by cache coherence problem? Describe various
protocols for cache coherence.
Or

Briefly explain various I/O performance measures.

2

(16)

66167

(16)

(a)

(i)

Describe the architecture of typical CMT processor.

(8)

(ii)

Discuss the design issues for simultaneous multithreading.

(8)

Or
(i)
Explain the architectural features of IBM cell processor in
detail.
(10)
Briefly compare SMT and CMP architectures.

(6)

11

(ii)

2

(b)

2

11

2

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11

15.

3

66167

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