Computer architecture

Topics: Error detection and correction, Computer memory, CPU cache Pages: 6 (1653 words) Published: April 14, 2014
EKT 422: Computer Architecture
Answer Scheme: Tutorial 2

1. A set associative cache consists of 64 lines or slot divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses. The cache is divided into 16 sets of 4 lines each. Therefore, 4 bits are needed to identify the set number. Main memory consists of 4K = 212 blocks. Therefore, the set plus tag lengths must be 12 bits and therefore the tag length is 8 bits. Each block contains 128 words. Therefore, 7 bits are needed to specify the word. Main memory address =

TAG
SET
WORD
8
4
7

2. For direct-mapped cache, a main memory address is viewed as consisting of three fields. List and define the three fields. One field identifies a unique word or byte within a block of main memory. The remaining two fields specify one of the blocks of main memory. These two fields are a line field, which identifies one of the lines of the cache, and a tag field, which identifies one of the blocks that can fit into that line.

3. For set-associative cache, a main memory address is viewed as consisting of two fields. List and define the two fields. One field identifies a unique word or byte within a block of main memory. The remaining two fields specify one of the blocks of main memory. These two fields are a set field, which identifies one of the sets of the cache, and a tag field, which identifies one of the blocks that can fit into that set

4. Consider a 32-bit microprocessor that has on-chip 16Kbyte four-way set-associative cache. Assume that cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE7F4 mapped. Block frame size = 16 bytes = 4 doublewords

Number of block frames in cache = 16 Kbytes = 1024
16 Bytes
Number of sets =Number of block frames =1024 = 256 sets
Associativity 4

Tag
Set
Offset
A B C D E
7 F
4

5. What is the general relationship among access time, memory cost, and capacity? Faster access time, greater cost per bit; greater capacity, smaller cost per bit; greater capacity, slower access time.

6. What are the differences among sequential access, direct access and random access? Sequential access: Memory is organized into units of data, called records. Access must be made in a specific linear sequence. Direct access: Individual blocks or records have a unique address based on physical location. Access is accomplished by direct access to reach the general vicinity plus sequential searching, counting, or waiting to reach the final location. Random access: Each addressable location in memory has a unique, physically wired-in addressing mechanism. The time to access a given location is independent of the sequence of prior accesses and is constant.

7. What is the different between DRAM and SRAM in term of characteristics such as speed, size and cost? SRAMs generally have faster access times than DRAMs. DRAMS are less expensive and smaller than SRAMs.

8. Explain why one type of RAM is considered to be analog and other digital. A DRAM cell is essentially an analog device using a capacitor; the capacitor can store any charge value within a range; a threshold value determines whether the charge is interpreted as 1 or 0. A SRAM cell is a digital device, in which binary values are stored using traditional flip-flop logic-gate configurations.

9. What are differences among EPROM, EEPROM and flash memory? EPROM is read and written electrically; before a write operation, all the storage cells must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation. Erasure is performed by shining an intense ultraviolet light through a window that is designed into the memory chip. EEPROM is a read mostly memory that can be written...
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