computer architecture

Topics: Computer, Address bus, Memory address Pages: 5 (399 words) Published: January 26, 2014
Quiz 3
Question 1
Design a microprocessor with the following specifications:
- the processor is connected to the main memory via the 32-bit address bus, 16-bit data bus, and control bus,
- the main memory is byte addressable,
- each instruction is of 16 bits,
- the state of the instruction cycle is specified by 2 flags P and Q (fetch sub-cycle = 00, execute sub-cycle = 10).
(a)

Show the micro-operations and control signals of the fetch and execute sub-cycles for the following instructions. M is main memory location and AC is accumulator. Instruction
LOAD M
STORE M
ADD M
MUL M

Remark
AC ← (M)
M ← (AC)
AC ← (AC) + (M)
AC ← (AC) * (M)

(b)

Draw a diagram showing the organization, data paths and control signals of that microprocessor that are involved in the fetch and execute sub-cycles for the instructions in part (a).

(c)

For each of the control signals in part (a), write the Boolean equation in terms of the control unit inputs that is used for hardwired implementation of the control unit.
Instruction
LOAD M
STORE M
ADD M
MUL M

Opcode
00
01
10
11

Decoder Output (I0 I1 I2 I3)
1000
0100
0010
0001
[10 marks]

Solution
Question 1
(a)
Fetch:
t1: MAR ← (PC)
t2: MBR ← Memory
PC ← (PC) + 2
t3: IR ← (MBR)

C2
C0, C5, Cread
C+2
C4

Execute (LOAD M):
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (MBR)

C14
C0, C5, Cread
C10

Execute (STORE M):
t1: MAR ← (IR(address))
MBR ← (AC)
t2: Memory ← (MBR)

C14
C11
C0, C12, Cwrite

Execute (ADD M):
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (AC) + (MBR)

C14
C0, C5, Cread
C6, C7, C9, Cadd

Execute (MUL M):
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: AC ← (AC) * (MBR)

C14
C0, C5, Cread
C6, C7, C9, Cmul

(4 marks)

(b)

C+2

+2

C14

Cadd
Cmul
P

Q

Cread Cwrite
(2 marks)
(c)
C0 = P • Q • t 2 + P • Q • (I0 + I1 + I 2 + I3 ) • t 2 C 2 = P • Q • t1

C4 = P • Q • t 3
C5 = P • Q • t 2 + P • Q • (I0 + I 2 + I3 ) • t 2
C6 = P • Q • (I 2 + I3 ) • t 3
C7 = P • Q • (I 2 + I3 ) • t 3
C9 = P • Q • (I 2 + I3 ) • t 3
C10 = P • Q • I0 • t 3
C11 = P • Q • I1 • t1
C12 = P • Q • I1 • t 2

C14 = P • Q • (I0 + I1 + I 2 + I3 ) • t1
C +2 = P • Q • t 2

C read = P • Q • t 2 + P • Q • (I 0 + I 2 + I3 ) • t 2 C write = P • Q • I1 • t 2
Cadd = P • Q • I 2 • t 3
C mul = P • Q • I3 • t 3
(4 marks)

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