Computer Architecture 2010 Ipu

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(Please write your Exam. Roll No.)

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ENP TERM EXAMINATION
THIRD SEMESTER (RCA), DECEMBER.
Paper Code.. BCA .2{)3 Paper ID .. 20203 Subject:

2010

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Compiller Archil(!('lIIre

Time.. 3 flours
Note.. Q. J is compulsory. Attempt One question from each unit.

Maximum Marks.. 75

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Q. 1. (a)

Design a 4.bit combinational circuit decrementer using four tLtliadder circuits.

(5 ) (5) (5) (5 ) (5) b

,-(.b-)--'Explaininterrupt cycle with an example. (c) What is an Input-Output interface? Why is it needed?

{dh Explain the concert of virtual memory. How isit implemented? (e--r What is associativ~' memory? Explain its architecture. r~ UNIT. I , Q. 2. (a) (b)

Describe Basic Instruction Set. Is it complete? J~stify,
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(8-5)

Register A holds the 8-bit binary 110 II 00 I. Delerrniile tqc B operand and the logic microoperation to be perforrried in order :
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to change the value in A to :
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(4 )

(i)

'OIIOIIOl

(ii) . 11 I 1110 1

Q.3.

, (a) Draw'a diagram of bus system for foLlrregisters with S-hi[ Clch using three-st-ate:lbu(fers and decoder, . .- ,-" f- -. (b) Expl,ain hard wired control unit organisation. I

(6-5)
(6)

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UNIT. II
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Q.4.

(a) Show the contents in he~adecimal of regi\sters PC, AR, DR, IR and sc or the basic computer when an I52 indirect instruction is fetched rrom memory and executed. The initial cJntent of PC is 7 FF. The colltellt ofmcmory at address 7FF is EA9F. The content of memory al address A 9F is OC35. The content of memory at address C 35 is FFFF, (h i Convert the following Polish notation:

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(5)

arithmetic

expressions

from infix to reverse

'-' (4'5) (3)

+ B :,: [C

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D + E * ( F + G)]
each of external and internal intel~rupts. statement:

(c..,) (jive three examples

Q.S.

(a} Write a program to evaluate the arithmetic
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;\ -- B + C *(0 * E - F)
. G+I-I*K
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(i)

Using a general register computer with one-address' i~structions.

Iii) (hi

\ ;"jng a sto'C,Korganiscd computer with zero-address operation instructions.', (8)

rile content of PC in the basic computer is 3AF. The content of AC . . i': 7 [('),

~he co~,Hent of memory at address 3 At:is 932E. The content
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(1"mcmory at add,ress 32E is 09Ac. The content of memory at address () /\('
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is 8 B () F,

W!1at is the instruction that will pe fetched and executed
(~'5)

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UNIT. III

Q.6.

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Dcscrihe the 'algorithm Il.l"i,~ned - magnitude

for division of two fixed-point representation.

binary numbers (6'S)

(h)

[)r;l\\' the block diagram of DMA contorller.

Also explain DMA (6)

tr:ll1sfer in computer system.
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Q. .,

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Design a parallcl priority intelTupt hardwareJor a system with eight intclTupt sources. (6) (6-5)

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,(p}-"Uiscuss handshaking approach for asynchronous data transfer. UNIT

- IV

Q.8..
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(a)

Construct al4096 x 8 main memory with 2048bytes each of RAM and ROM using 128 x 8 RAM chips and 512 x 8 ROM chips. List

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(h)

also the memory address map. Ocscrihe ,.memory hierarchy in computer systcm.

(7-5)
(5)

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Q.9

(a) Consider the follo\'ving page reference stream:

L 2, 3. 4, 5, 6,2, L 2, 3, S, 6, 3, 2, 4,\2,6. If a process is allocated four frames, how many page faults would occur if page replacements (i) FIFO (ii) LRU are done using the (8)

, b) The logical address spacein a computer system consists.of 128 .. . segments.

Each segmentcan have upto 32 pages 'of4K\yords in
the logical and physical address fnrmuts,
(4-5)

'-.J-

each. Physical memory consists of 4K blocks (.)f4K words in each. Formulate

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