Computer and Adders

Topics: Binary numeral system, Computer arithmetic, Computer Pages: 20 (3829 words) Published: July 13, 2013
Dept. of Electrical and Computer Engineering University of Minnesota, Minneapolis, MN 55455, USA E-mail: Keshab K. Parhi

Abstract - This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wtfa to Wtmux where tfa and tmux , respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carrygeneration component is the critical component in redundant-to-binary conversion and binary addition. It is shown that, if the word-length, W , is a power of two, then all carry signals can be generated in log2 Wtmux time using W (log2 W ? 1) + 1 multiplexers using a tree-type converter. It is shown that fastest binary addition can be performed using (Wlog2 W + 1) multiplexers in time (log2 W + 1)tmux . If the speci ed converter latency is greater than log2 Wtmux, then a family of converters using fewest multiplexers can be designed based on carry-select approach. It is shown that the power consumption in carry-select adders is minimized by increasing the number of segments in the adder. Binary addition is one of the primitive operations in computer arithmetic. The well known ripple carry adder can add two W -bit binary numbers using W binary full adders with latency Wtfa where tfa represents the binary full adder delay 1]. Fast addition can be carried out using various fast adders such as carry-select adder 2] or binary look-ahead adder 3]. These fast adders can also be implemented e ciently using multiplexers only. Another approach to designing much faster binary adders involves exploiting the equivalence between redundant-to-binary (RB) conversion and binary addition 4]. The proposed approach involves interpreting the bits of the adder operands as redundant digits which can be converted to a binary number using fast RB converters. Fast RB converters can also be designed by using variations of known fast binary adder algorithms. Since the basic operation involved in RB conversion is much simpler than binary addition, the proposed approach


leads to much faster and smaller binary adders. The use of redundant arithmetic in fast binary arithmetic was rst published in 5]. Many approaches to RB conversion have been published in 6]- 9]. The equivalence between binary addition and RB conversion is now clearly understood. Thus, algorithms known for one problem can be directly applied for the other. This paper considers two types of RB converters referred to as tree-based and carry-select which are obtained exactly in the same way as binary look-ahead and carry-select adders are designed. In this paper, it is shown that fastest binary adders can be designed using tree-based RB converters obtained using look-ahead approaches 3] 10]. It is shown that fastest binary addition can be performed using (Wlog2 W +1) multiplexers in time (log2W +1)tmux. If fastest design is not needed, then a family of adders can be designed using tree-based and carry-select converters. These adders can be analyzed for power consumption and the design with least power can be selected.

Consider the operation X = A + B where X = xW ?1 :::x0 , A = aW ?1 :::a0 , and B = bW ?1 :::b0 , represent W bit binary numbers. This addition can be expressed as X = A + B = A ? (?B ) = A ? (B + 1) = (A ? B ) + (?1). The negative of B is rst expressed in terms of sum of one's complement which corresponds to bit inversion and 1 in the least signi cant bit (lsb) position. The composite number (A ? B ) can be interpreted as a redundant number where each...
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