Compiler Design 2

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Refreshing ... Uncensored ... Groundbreaking …. The Dr. Wang’s original lecture:

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Tutorial of Design Compiler

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Introduction Setting Up the Tutorial Graphical Interface The Alarm Clock Design Setting Design Environment Setting Design Constraints Overview of Optimization Phases Analysis of Report DC Tutorial - 2

Introduction
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Introduction

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The Synthesis Process Design Compiler Products Synthesis Programs and Tools Design Styles Input and Output Formats User Interfaces Script Files

DC Tutorial - 4

The Synthesis Process
Start Rewrite Verilog Code Read in Design Set Attributes Set Realistic Timing Goal Check Design Errors No Yes Fix Bugs Change Constraints Modify Compile Attributes Ungroup Design Blocks

The DC Products
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DC Professional
– No multi-frequency clocking, latch-based time borrowing, pipeline re-timing, critical path resynthesis, in-place optimization, and incremental editing

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DC Expert
– Include features for maximizing performance

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FPGA Compiler
– Targets only FPGA technology

Optimize No Good? Yes Done
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DC Tutorial - 6

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Synthesis Tools
HDL Design Analyzer HDL Compilers DesignWare DesignWare Developer

Architectural Optimization
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Architectural Optimization Gate-Level

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Design Analyzer Logic Optimization Design Compilers Cell Library

Library Compiler

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Arithmetic Optimization Timing and Area-Based Resource Sharing Sub-expression Removal Constraint-Driven Resource Selection Inference of Synthetic Part (DesignWare) For more information – HDL Compiler for Verilog Reference Manual

Optimized Gate-level Netlist
DC Tutorial - 7 DC Tutorial - 8

DesignWare
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DesignWare Developer

Provide a library of high-level design components
– Adders, Multiplier, etc.

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The HDL compiler will select the proper components for you based on your timing and area goals See Documentation Collection (open collection) – Synopsys DesignWare 1997.01

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Create DesignWare Libraries

DC Tutorial - 9

DC Tutorial - 10

DC Products
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Cell Library
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Library of basic cells used by DC
– AND, OR, XOR, etc.

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Optimize your design at the gate level Using selected cell libraries

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For FPGA compiler, it may contain more complex cells
– Xilinx CLBs, IOBs, etc.

DC Tutorial - 11

DC Tutorial - 12

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Library Compiler

Design Styles

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Yes, you can create your own cell libraries

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Hierarchical or Flatten Combinational or Sequential

DC Tutorial - 13

DC Tutorial - 14

Input Formats
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Output Formats
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VHDL Verilog PLA & EDIF 2.00 Xilinx XNF

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Synopsys binary format (.db files) VHDL Verilog EDIF 2.00 Equation, LSI Logic, Mentor Graphics, PLA, state table, Tegas formats Xilinx XNF format

DC Tutorial - 15

DC Tutorial - 16

User Interfaces
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Scripts
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shell> dc_shell
– – – – – – – – – unix-like command shell dc_shell> quit dc_shell> cd my_dir dc_shell> alias wv write -f verilog dc_shell> pwd dc_shell> history n dc_shell> list -command dc_shell> man dc_shell> sh “lpr ”

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shell> design_analyzer
– graphical interface
DC Tutorial - 17

A set of command can be put together into a file called “script” Then, you don’t need to re-type some the commands again and again when using the dc_shell Scripts for this tutorial will be provided for your reference You can run them when you are home without the X-window capability DC Tutorial - 18

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Locate Documentation
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shell> design_analyzer & select Help --> On-Line Documentation …. Ignore the square window with “Titles” – select Cancel to close it – focus on the one with “File, Edit, View …” select File --> Open Collection select Synopsys Synthesis Tools 1997.01 and then click OK select Documents Formatted for Printing and then click Open In the “File, Edit, View …” window, now you can select a list...
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