# Cmos Lna Design Techniques

**Topics:**Inductor, Transistor, Impedance matching

**Pages:**13 (2542 words)

**Published:**October 11, 2009

X/Ku Band CMOS LNA Design Techniques

Bagher Afshar, Ali M. Niknejad Berkeley Wireless Research Center, Dept. of EECS, UC Berkeley, Berkeley, CA 94704, USA

Abstract— This paper reports two 11 GHz low-noise ampliﬁers (LNA) in 0.18µm CMOS technology. A cascade two stage LNA achieves 12 dB of power gain, 3.5 dB of noise ﬁgure, and an input/output match of −15 dB/−27 dB at 11GHz, while consuming 28mA from 1.8V supply. The second LNA is a modiﬁed cascode ampliﬁer and it achieves 8 dB of gain, 3.1 dB of noise ﬁgure, and an input/output match of −12 dB/−15 dB at 11GHz, consuming 18mA from the 1.8V supply. The paper also discusses design considerations such the effects of layout on frequency tuning and noise.

iout Vbias Lg Vin Rs Ls M1 Rs Vin M2

Lg gmVgs i2ng gg Cgs Vgs

iout i2nd

Ls

I. I NTRODUCTION Rapid evolution of wireless communication has resulted in a continuous trend towards utilizing higher frequencies for wideband communication applications. CMOS technology is of major interest for its low cost and high level of integration. While much research has been done on integrating cellular and WLAN transceivers in CMOS and SiGe technology [1], very little work has been done at 10GHz (X-band, Ku-band). There are many interesting and important commercial applications in this frequency band, such as the satellite communication receivers for entertainment and high speed internet access. Current microwave receivers at this frequency are not only physically large, but are also expensive. Realization of such devices in standard CMOS will enable wider commercial adoption. On the other hand much research activity has recently focused on higher frequencies, such as the 60GHz band [2] and the 77GHz band [3]. Unfortunately microwave transmission-line based design techniques do not scale to relatively lower frequencies like 10GHz. Due to area constrains, circuits at these frequencies must employ relatively small lumped passive components, such as inductors ∼ 250pH , and such small reactances must be realized on-chip. As we shall see, realization of such inductors is challenging due to parasitic inductance of the layout. II. D ESIGN FOR L OW N OISE A simpliﬁed small signal model for a simpliﬁed inductive degenerated cascode LNA is shown in Fig. 1. Ignoring Cgd , the input impedance Zin is given by Zin ∼ = gm Ls 1 + s(Ls + Lg ) + + rLg sCgs Cgs (1)

Fig. 1. (a) Simpliﬁed cascode LNA. (b) Small-signal model of (a) (M2 is ignored for simplicity).

Which can be simpliﬁed to [4] rLg + rt g mM 2 F ∼1+ + ΓαgmM 1 Rs 1 + = Rs 10gmM 1 f fT 2

(3) γg L ·ω where Γ = αgd0 , α = 1 + gmb , rLg = QgL , RL is the gm m g load resistance and rt = rg + rs + ri accounts for total gate resistance including induced gate noise. At a given frequency, given lossless feedback and matching networks, selection of the optimum device width and optimum bias voltage at each frequency results in an input match and an overall noise ﬁgure of Fmin , the minimum noise ﬁgure of the circuit [5]. Unfortunately, practical inductors have ﬁnite quality factor, requiring a careful trade-off between the input match and the noise ﬁgure. III. LNA C IRCUIT D ESIGN The simpliﬁed schematics of the single-stage cascode and two-stage cascade LNA’s are shown in Fig. 2 and Fig. 3. Both topologies utilize inductive degeneration for input matching to 50Ω. Degeneration also improves the linearity by forming a negative series-series feedback. For the cascade two-stage design, the second stage also employs inductive degeneration to improve the linearity of the ampliﬁer (rather than for matching). In Fig. 3, the output of ﬁrst stage will resonate with the total capacitance connected to the drain of M3 . The advantage of using a single transistor for the ﬁrst stage is to lower the overall noise contribution of the input stage. In single-stage LNA of Fig. 2, the impedance seen through the drain of M1 without considering Lr...

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