Cmos Inverter
Lecture 4 CMOS Inverter
Professor Sunil Bhave p CU School of Electrical and Computer Engineering February 8, 2010
Inverters I t
DC Analysis
Operating regions and voltage transfer curve Logic levels and noise margins
Transient Analysis - delay Power P
Objectives Obj ti
We have studied how a transistor can be viewed as a switch (switchview) We have derived the I-V model for a transistor Now with this simple model, we analyze the “electrical” properties of a CMOS inverter Noise Margin Delay Power Two outcomes: Analysis ability Understand concepts (intuition)
Reliability― Noise in Digital Integrated Circuits
v(t) i(t) ()
V DD
Inductive coupling
Capacitive coupling
Power and ground noise
DC Operation Voltage Transfer Characteristic
V(out)
Mapping between analog and digital signals
V out Slope = -1
V
OH
f V(y)=V(x)
VOH = f(VOL) VOL = f(VOH) VM = f(VM)
“ 1”
V OH V IH Undefined Region V
V
OH
VM Switching Threshold V OL V OL V OH V(in)
IL
Slope = -1 V OL V IL V IH V in
“ 0”
V
OL
Nominal Voltage Levels
Definitions D fi iti
VM VIL VOL VIH VOH
Definitions D fi iti
VM – Vout=Vin VIL – Slope = -1 VOL – Vout @ VIH VIH – Slope = -1 VOH – Vout @ VIL
Regenerative Property out v3 v1 fin v(v) f (v)
Regenerative Property v0 v1 v2 v3 v4 v5 v6
out v3 v1 v3 f (v)
V (Volt)
3
fin v(v)
A chain of inverters
5 v0
1
v1
v2 6 8 10
v2
0 Regenerative
v
in
v0
2 Non-Regenerative
v
in
Simulated response
21
0
2
4 t (nsec)
Noise M N i Margins i
How much noise can a gate input see before it does not recognize the input?
Noise B d t N i Budget
Allocates gross noise margin to expected sources of noise Sources: supply noise, cross t lk S l i talk, interference, offset Differentiate between fixed and proportional Diff ti t b t fi d d ti l noise sources
Key Reliability Properties
Absolute noise margin values are deceptive a floating node
Professor Sunil Bhave p CU School of Electrical and Computer Engineering February 8, 2010
Inverters I t
DC Analysis
Operating regions and voltage transfer curve Logic levels and noise margins
Transient Analysis - delay Power P
Objectives Obj ti
We have studied how a transistor can be viewed as a switch (switchview) We have derived the I-V model for a transistor Now with this simple model, we analyze the “electrical” properties of a CMOS inverter Noise Margin Delay Power Two outcomes: Analysis ability Understand concepts (intuition)
Reliability― Noise in Digital Integrated Circuits
v(t) i(t) ()
V DD
Inductive coupling
Capacitive coupling
Power and ground noise
DC Operation Voltage Transfer Characteristic
V(out)
Mapping between analog and digital signals
V out Slope = -1
V
OH
f V(y)=V(x)
VOH = f(VOL) VOL = f(VOH) VM = f(VM)
“ 1”
V OH V IH Undefined Region V
V
OH
VM Switching Threshold V OL V OL V OH V(in)
IL
Slope = -1 V OL V IL V IH V in
“ 0”
V
OL
Nominal Voltage Levels
Definitions D fi iti
VM VIL VOL VIH VOH
Definitions D fi iti
VM – Vout=Vin VIL – Slope = -1 VOL – Vout @ VIH VIH – Slope = -1 VOH – Vout @ VIL
Regenerative Property out v3 v1 fin v(v) f (v)
Regenerative Property v0 v1 v2 v3 v4 v5 v6
out v3 v1 v3 f (v)
V (Volt)
3
fin v(v)
A chain of inverters
5 v0
1
v1
v2 6 8 10
v2
0 Regenerative
v
in
v0
2 Non-Regenerative
v
in
Simulated response
21
0
2
4 t (nsec)
Noise M N i Margins i
How much noise can a gate input see before it does not recognize the input?
Noise B d t N i Budget
Allocates gross noise margin to expected sources of noise Sources: supply noise, cross t lk S l i talk, interference, offset Differentiate between fixed and proportional Diff ti t b t fi d d ti l noise sources
Key Reliability Properties
Absolute noise margin values are deceptive a floating node