Cadence Tt

Topics: Electronic design automation, Cadence Design Systems, Verilog Pages: 4 (473 words) Published: April 24, 2013
Cadence and Specman
ACP Summer School, June 2011

Reuven Naveh
Cadence (rnaveh@cadence.com)

© 2011 Cadence Design Systems, Inc. All rights reserved worldwide.

1

Cadence
 One of three major EDA companies  Established in 1988, over 4000 employees  Wide variety of areas and products in

hardware design


Virtuoso, Encounter, Allegro…

 We will focus on functional verification
 

Incisive platform Mainly „Incisive Enterprise Specman Elite‟ (AKA „Specman‟)

© 2011 Cadence Design Systems, Inc. All rights reserved worldwide.

2

Functional Verification
 Why so important?
 

Prevents much costly bugs at the post-silicon level Takes more than half of the effort of hardware projects

 Formal verification

 

Attempts to prove the correctness of a given specification Solvers are used to find a solution Cadence tool – IFV (Incisive Formal Verifier)

 Simulation based verification
  

Tests the hardware through simulation Constraints are used to create legitimate random stimuli Verification languages: SystemVerilog (IEEE 1800), e (IEEE 1647) © 2011 Cadence Design Systems, Inc. All rights reserved worldwide. 3

Coverage Driven Verification Environment
Verification Environment
Stimulus stimulus Stimulus Scenarios Scenarios Scenarios

Automatic Stimulus Generation

Physical Layer

Data and Assertion Checkers

Device
Generation Self Checking

Coverage Monitor
Coverage

Specman
 Cadence’s major test bench automation

tool  Developed by Verisity in the nineties  Being used in the biggest and most advanced verification environments  Supports all aspects of coverage-drivenverification  Can be attached to any simulator  Uses e verification language © 2011 Cadence Design Systems, Inc. All rights reserved worldwide. 5

e Language (some examples)
 “AOP”
//environment code struct data { len:uint; kind:[SMALL,BIG];

keep kind == SMALL => len in [10..20];
keep kind == BIG => len in...
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