Branch Delay

Topics: Instruction processing, Branch predictor, Death Penalty Pages: 6 (1747 words) Published: August 26, 2013
Delayed Branch
A technique for minimizing the effect of control dependencies is to separate the point where the branch operation takes effect from the branch tests. The branch instruction performs a test on a branch condition. If the test succeeds, the PC is modified, but the modification does not take effect immediately. This delayed branch allows one or more instructions following the branch to be executed in the pipeline whether the branch is taken or not. In the MIPS CPU, the branch operation is delayed by one instruction. The MAL assembler hides the delayed branch by inserting an instruction after each branch or jump. The instruction following a branch or jump is called the delay slot. By default the assembler inserts an instruction which does nothing, a no-op. In previous sections describing the branch instruction, it was stated that the PC was incremented when the branch was fetched and therefore the branch offset is relative to the instruction after the branch. The delayed branch means that the instruction following the branch is always executed before the PC is modified to perform the branch.

The delayed branch is a difficult topic to grasp. In the DLX 5-stage pipeline we have found it easy to misunderstand the purpose of filling the branch delay slot with a single necessary instruction. Our focus is to remove the mystery of delayed branches with examples and explanations that clarify the topic. We will consider the case where machines with delayed branches have a single instruction delay, as the Hennessey and Patterson book explains in great detail. In some examples, it is hard to figure out why certain instructions should be placed after the branch. Also, it might be confusing to some that only one instruction would absorb the stall that would normally occur while a branch instruction is executed.  With the help of key term definitions, it will be easier to learn how to unroll a loop as well as reschedule it. Then, determine which instruction best fills the branch delay slot. Keep the following guidelines in mind while solving the problems. * Each time a branch is encountered by the compiler place a useful instruction in the following slot. * What to put in the slot?

* Instruction from before the branch
- Branch must not depend on moved instruction
- Always improves performance
* From branch target
- Must be OK to execute moved instruction when the branch is not taken - Improves performance when branch is taken
* From fall through
- Must be OK to execute moved instruction when branch is taken - Improves performance when branch is not taken

Branch delay slots
Some early processors were not able to squash the instruction following a branch in the hardware and required the compiler to insert a NOOP - an instruction that does nothing into the program following every branch. Thus instead of emitting this:| mult $4, $2, $1add $3, $4, $5retsub $4, $6, $7| the compiler would emit:| mult $4, $2, $1add $3, $4, $5retor $1, $1, $1sub $4, $6, $7| Note that or $1, $1, $1

is an effective NOOP - it changes nothing!|
|
The instruction following the branch is said to be in the branch delay slot. It was soon realised that, since the instruction in this slot has progressed well down the pipeline anyway, if it was guaranteed that it would be executed, some improvement in performance would result. The compiler is asked to move an instruction that must be executed which precedes the branch into the branch delay slot where it will be executed while the branch target is being fetched. Current RISC machines will have a one-instruction branch delay slot - occasionally two.This is an example of the modern trend in computer architecture - to expose more details of the underlying machine to the compiler and let it generate the most efficient code. In this case, it is...
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