Low Power Booth Multiplier by Effective Capacitance Minimization
P. Nageshwar Reddy
Dr. Damu Radhakrishnan
Stu. in SUNY, New Paltz, NY
Prof. in SUNY, New Paltz, NY
Abstract: In this paper we present an energy efficient parallel multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in our research. The effective capacitance is the product of capacitance and switching activity. Hence to minimize the effective capacitance in our design, we decided to ensure that the switching activity of nodes with higher capacitances is kept to a minimum. This is achieved in our design by wiring the higher switching activity signals to nodes with lower capacitance and vice versa for the 4:2 compressor and full adder cells, assuming the initial probability of each partial product bit as 0.25. This reduced the overall switching capacitance, thereby reducing the total power consumption in the multiplier. Power analysis is done by synthesizing our design on Spartan-3E FPGA and used XPower Analyzer tool that is provided in ISE Xilinx 10.1. The dynamic power for our 16×16 multiplier was measured as 360.74mW, and the total power 443.31mW. This is 17.4% less compared to the most recent design. Also we noticed that our design has the lowest power-delay product compared to the multiplier presented in the literature.
Index Terms- Booth multiplier, Effective capacitance, 4:2 compressor.
A multiplier is the most frequently used fundamental arithmetic unit in various digital systems such as computers, process controllers and signal processors. Thus it has become a major source of power dissipation in these digital systems. With the exponential growth of portable systems that are operated on batteries, power reduction has become one of the primary design constraints in recent years. In the present era, each and every electronic device is implemented using CMOS technology. The three major sources of power dissipation in digital CMOS circuits are dynamic, short circuit and leakage . Generally, power reduction techniques aim at minimizing all the above mentioned power dissipation sources but our emphasis is on dynamic power dissipation as it dominates other power dissipation sources in digital CMOS circuits. The switching or dynamic power dissipation occurs due to the charging and discharging of capacitors at different nodes in a circuit . The average dynamic power consumption of a digital circuit with N nodes is given by:
where VDD is the supply voltage, Ci is the load capacitance at node i, fCLK is the clock frequency and αi is the switching activity at node i. The product of switching activity and load capacitance at a node is called effective capacitance. Assuming only one logic change per clock cycle, the switching activity at a node i can be defined as the probability that the logic value at the node changes (0->1 or 1->0) between two consecutive clock cycles. For a given logic element, the switching activity at its output(s) can be computed using the probability of its inputs and is given by:
where and denote the probability of occurrence of a ‘one’ and ‘zero’ at node i respectively. When Pi = 0.5, the switching activity at a node is maximum and it decreases as it goes towards the two extreme values (i.e. both from 0.5 to 0 and 0.5 to 1). The two main low power design strategies for dynamic power reduction are based on (i) supply voltage reduction and (ii) the effective capacitance minimization. The reduction of supply voltage is one of the most aggressive techniques because the power savings are significant due to the quadratic dependence on VDD. Although such reduction is usually very effective, it increases leakage current in the transistors and also decreases circuit speed. The minimization of effective switching capacitance involves reducing switching activity or node capacitance. The node capacitance depends...
Please join StudyMode to read the full document