Automata Theory and Discuss Gate

Only available on StudyMode
  • Download(s) : 162
  • Published : October 3, 2012
Open Document
Text Preview
CS-Paper Code-B

GATE 2011

www.gateforum.com

Q. No. 1 – 25 Carry One Mark Each 1. The simplified SOP (Sum of Product) P + Q + R . P + Q + R . P + Q + R is form of the Boolean expression

)( (A) (PQ + R )
QR

(

)(

)

(B) P + QR

(

)
)(

(C) PQ + R

(

)

(D) (PQ + R )

Answer: - (B) Exp: P
0 00 01 1 11 1 10 1

f = P+R P+Q = P + QR

(

)

1

Alternate method

(P + Q + R ) . (P + Q + R ) . (P + Q + R ) = (P + Q + R ) . (P + Q + R ) . (P + Q + R ) = P QR + P QR + P QR = P Q R + R + P QR = P Q + P QR =P Q + QR = P ( Q + R) = P + Q R

(

)

(

)

2.

Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate? (A) (B)

(C) Answer: - (D)

(D)

Exp: - All options except option ‘D’ gives EX-NOR gates 3. The minimum number of D flip-flops needed to design a mod-258 counter is (A) 9 Answer: - (A) Exp: - 2n ≥ 258 ⇒ n = 9 4. A thread is usually defined as a ‘light weight process’ because an operating system (OS) maintains smaller data structures for a thread than for a process. In relation to this, which of the followings is TRUE? (B) 8 (C) 512 (D) 258

© All rights reserved by Gateforum Educational Services Pvt. Ltd. No part of this document may be reproduced or utilized in any form without the written permission. Discuss GATE 2011 question paper at www.gatementor.com. 1

CS-Paper Code-B

GATE 2011

www.gateforum.com

(A) On per-thread basis, the OS maintains only CPU register state (B) The OS does not maintain a separate stack for each thread (C) On per-thread basis, the OS does not maintain virtual memory state (D) On per thread basis, the OS maintains only scheduling and accounting information Answer: - (A) 5. K4 and Q3 are graphs with the following structures K4

Q3

Which one of the following statements is TRUE in relation to these graphs? (A) K4 is planar while Q3 is not (C) Q3 is planar while K4 is not Answer: - (B) Exp: K4 (B) Both K4 and Q3 are planar (D) Neither K4 not Q3 is planar Q3

∴ Both K4 and Q3 are planar

6.

If the difference between the expectation of the square of random variable E X2  and the square of the expectation of the random variable E X2  is    

(

)

(

)

denoted by R then (A) R = 0 Answer: - (C) (B) R0

7.

The lexical analysis for a modern computer language such as Java needs the power of which one of the following machine models in a necessary and sufficient sense? (A) Finite state automata (B) Deterministic pushdown automata (C) Non-Deterministic pushdown automata

© All rights reserved by Gateforum Educational Services Pvt. Ltd. No part of this document may be reproduced or utilized in any form without the written permission. Discuss GATE 2011 question paper at www.gatementor.com. 2

CS-Paper Code-B
(D) Turing machine Answer: - (A)

GATE 2011

www.gateforum.com

Exp: - Lexical Analysis is implemented by finite automata

8.

Let the page fault service time be 10ms in a computer with average memory access time being 20ns. If one page fault is generated for every 106 memory accesses, what is the effective access time for the memory? (A) 21ns (B) 30ns (C) 23ns (D) 35ns

Answer: - (B)

Exp: - P = page fault rate EA = p × page fault service time + (1 − p ) × Memory access time = 1 1  × 10 × 106 + 1 − 106 106    × 20 ≅ 29.9 ns 

9.

Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory? (A) Immediate Addressing (B) Register Addressing

(C) Register Indirect Scaled Addressing (D) Base Indexed Addressing Answer: - (D) Exp: - Here 20 will act as base and content of R2 will be index...
tracking img