Anjan Ass 7

HOMEWORK 7 ANJAN REDDY Student Id:700624059

8.20 Assuming a 1-KB page size, what are the page numbers and offsets forthe following address references (provided as decimal numbers):
a. 3085
b. 42095
c. 215201
d. 650000
e. 2000001

ANS:
Page size =2n =1024 Bytes = 210 B
# of bits in offset part (n) =10
Solution steps:
1. Convert logical address: Decimal Binary
2. Split binary address to 2 parts (page #, Offset), offset : n digits
3. Convert offset & page#: Binary Decimal

Logical address
(decimal)

Logical address
(binary)

Page #
(22 bits) (binary)

Offset
(10 bits)
(binary)

Page # decimal Offset decimal 3085
00000000000000000000110000001101

0000000000000000000011

0000001101
3
13
42095
00000000000000001010010001101111
0000000000000000101001
0001101111
41
111
215201
00000000000000110100100010100001

0000000000000011010010
0010100001
210
161
650000
00000000000010011110101100010000
0000000000001001111010
1100010000
634
784
2000001
00000000000010000000000000000001
0000000000001000000000
0000000001
512
1
8.23 Consider a logical address space of 256 pages with a 4-KB page size, mapped onto a physical memory of 64 frames.
a. How many bits are required in the logical address?
b. How many bits are required in the physical address?

ANS:
a)m=?
number of pages = 2m-n
Size of logical address space = 2m = number of pages × page size
Page size=2n
Page size = 4KB = 4 * 1024 =4096=212
2m = 256 * 4096 2m = 28 × 212 2m =220
Therefore,m=20 bit

b) Let (x) is number of bits in the physical address x =???
Size of physical address space = 2x
Size of physical address space = # of frames × frame size (frame size = page size )
Size of physical address space = 64 × 4096 2x =26 × 212 2x = 218 number of required bits in the physical address x =18 bit

8.25 Consider a paging system with the page table stored in memory.
a. If a memory reference takes 50 nanoseconds, how long does a paged memory reference take?
b. If we add TLBs, and 75 percent of all page-table references are found in the TLBs, what is the effective memory reference time? (Assume that finding a page-table entry in the TLBs takes 2 nanoseconds, if the entry is present.)

ANS:
a) 100 nanoseconds: 50ns to access the page table, 50ns to access the word in memory.
b) 64.5 nanoseconds: 75% of the time it's 50 ns, and the other 25% of the time it's 100ns, so the equation is:
2+ (75% * TLB hit-time) + (25% * TLB miss-time) = 2 + (75% * 50) + (25% * 100) = 64.5 ns

8.29 What is the purpose of paging the page tables?

ANS:
In certain situations the page tables could become large enough that by paging the page tables, one could simplify the memory allocation problem and also enable the swapping of portions of page table that are not currently used.In order to reduce the size of page tables directly to physical memory, 2-level paging is used.

9.21 Consider the following page reference string:
7, 2, 3, 1, 2, 5, 3, 4, 6, 7, 7, 1, 0, 5, 4, 6, 2, 3, 0 , 1.
Assuming demand paging with three frames, how many page faults would occur for the following replacement algorithms?
• LRU replacement
• FIFO replacement
• Optimal replacement

ANS:
LRU replacement algorithm: Page faults:18
FIFO replacement algorithm: Page faults: 17
Optimal replacement algorithm: Page faults: 13

9.27 Consider a demand-paging system with the following time-measured utilizations: CPU utilization 20%
Paging disk 97.7%
Other I/O devices 5%
For each of the following, indicate whether it will (or is likely to) improve
CPU utilization. Explain your answers.
a. Install a faster CPU.
b. Install a bigger paging disk.
c. Increase the degree of multiprogramming.
d. Decrease the degree of multiprogramming.
e. Install more main memory.
f. Install a faster hard disk or multiple controllers with multiple hard disks. g. Add prepaging to the page-fetch algorithms.
h. Increase the page size.

ANS:

The system obviously is spending most of its time paging, indicating over-allocation of memory. If the level of multiprogramming is reduced resident processes would page fault less frequently and the CPU utilization would improve. Another way to improve performance would be to get more physical memory or a faster paging disk.

a) Get a faster CPU: This will likely have no effect. The limiting factor is available memory per program.
b)Get a bigger paging disk: This should have no affect really.
c)Increase the degree of multiprogramming: This typically decreases CPU utilization because less memory is available to each program and the chances of page faults increase.
d)Decrease the degree of multiprogramming: This typically increases CPU utilization by keeping more of the working set of each program in memory, thereby reducing the number of page faults.
e) Install more main memory: Likely to improve CPU utilization as more pages can remain resident and not require paging to or from the disks.
f)Install a faster hard disk, or multiple controllers with multiple hard disks: This will decrease the time spent waiting for pages to be brought in so it’ll increase responsiveness of the system, but since the CPU context switches to other programs anyway, this might not increase CPU utilization that much, if at all. It’s possible that the faster page retrieval limits the number of context switches but, thrashing will still be occuring.
g)Add prepaging to the page fetch algorithms - This is increase CPU utilization by avoiding page faults by having the pages pulled into memory before they’re needed.
h)Increase the page size - Increasing the page size will result in fewer page faults if data is being accessed sequentially. If data access is more or less random, more paging action could ensue because fewer pages can be kept in memory and more data is transferred per page fault. So this change is as likely to decrease utilization as it is to increase it.

9.30 A page-replacement algorithm should minimize the number of pagefaults. We can achieve this minimization by distributing heavily usedpages evenly over all of memory, rather than having them compete fora small number of page frames. We can associate with each page framea counter of the number of pages associated with that frame. Then,to replace a page, we can search for the page frame with the smallestcounter.
a. Define a page-replacement algorithm using this basic idea. Specifically address these problems:
i. What is the initial value of the counters? ii. When are counters increased? iii. When are counters decreased? iv. How is the page to be replaced selected?
b. How many page faults occur for your algorithm for the following reference string with four page frames?
1, 2, 3, 4, 5, 3, 4, 1, 6, 7, 8, 7, 8, 9, 7, 8, 9, 5, 4, 5, 4, 2.
c. What is the minimum number of page faults for an optimal pagereplacement strategy for the reference string in part b with fourpage frames?

ANS:
a) Define a page-replacement algorithm addressing the problems of:
i. Initial value of the counters = 0. ii. Counters are increased whenever a new page is associated with that frame. iii. Counters are decreased whenever one of the pages associated with that frame is no longer required. iv. How the page to be replaced is selected by finding a frame with the smallest counter.
Use FIFO for breaking ties.
b) 14 page faults
c) 11 page faults