Analyzing Alloy Constraints Using an Smt Solver: a Case Study

Only available on StudyMode
  • Topic: Formal methods, Model checking, Boolean satisfiability problem
  • Pages : 21 (7422 words )
  • Download(s) : 60
  • Published : June 18, 2011
Open Document
Text Preview
Analyzing Alloy Constraints using an SMT Solver: A Case Study Aboubakr Achraf El Ghazi
Karlsruhe Institute of Technology Karlsruhe, Germany

Mana Taghdiri
Karlsruhe Institute of Technology Karlsruhe, Germany

elghazi@kit.edu ABSTRACT
This paper describes how Yices, a SAT Modulo theories solver, can be used to analyze the address-book problem expressed in Alloy, a first-order relational logic with transitive closure. Current analysis of Alloy models – as performed by the Alloy Analyzer – is based on SAT solving and thus, is done only with respect to finitized types. Our analysis generalizes this approach by taking advantage of the background theories available in Yices, and avoiding type finitization when possible. Consequently, it is potentially capable of proving that an assertion is a tautology – a capability completely missing from the Alloy Analyzer. This paper also reports on our experimental results that compare the performance of our analysis to that of the Alloy Analyzer for various versions of the address book problem.

mana.taghdiri@kit.edu
SAT via bit blasting, they can be analyzed with respect to only a few bits. Consequently, Alloy offers limited support for arrays and numerical constraints. This motivated our project: to analyze Alloy models using an SMT solver rather than a SAT solver. SMT solvers are particularly attractive because they can efficiently prove a rich combination of decidable background theories without sacrificing completeness or full automation. Furthermore, their capability to generate satisfying instances as well as unsatisfiable cores[23] (offered only by some SMT solvers) supports Alloy’s lightweight and easy-to-use approach. This paper describes the first step of our project. It reports on a case study where an SMT solver, namely Yices[7], is used to analyze an Alloy model, namely the address book problem[16]. To our knowledge, this is the first attempt to analyze a rich relational logic using an SMT solver. We have checked several assertions in three different versions of the address book model: (1) the basic model where each name is mapped to at most one address, (2) the hierarchical model where groups and aliases are allowed, and (3) the acyclic model where no name is mapped to itself. Although the models are small, their constraints are typical of Alloy formulas; they include many of the Alloy constructs that are often used in various applications. This case study is performed in the context of a bigger project in which Alloy specifications will be automatically translated to an SMT logic and solved by an SMT solver. Therefore, we ensure that our formulation of the addressbook problem is loyal to its Alloy model. However, in order to mitigate the bounded-analysis problem of Alloy, we avoid type finitization as much as possible. This approach poses challenges in handling some Alloy constructs such as abstract signatures, multiplicity keywords on a relation’s range, and set membership. Our translation of these constructs involves the use of Yices λ-expressions and quantifiers. Consequently, it is possible for the Yices analysis to be unsound. In such cases, the Yices output will be preceded by the word ”unknown”, and should be checked for validity. In this case study, however, the unsatisfiable outputs were always definite, meaning that the assertions were soundly proven correct and the satisfying instances, although preceded by ”unknown”, were real counterexamples. Since the Alloy logic is undecidable, type finitization is inevitable for some Alloy constructs. In particular, our encoding of transitive closure requires type finitization. However, even when finitization is required, it can be done ondemand: it is sufficient to finitize only the types to which those certain constructs are applied; the other types can

Keywords
Formal specification, SAT Modulo Theories, Yices, Relational logic, Alloy, Modeling languages

1. INTRODUCTION
Alloy[15] is a first order, declarative language that is...
tracking img