An Extendible Mips–I Processor Kernel in Vhdl for Hardware/Software Co-Design

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An extendible MIPS–I processor kernel in VHDL for hardware/software co-design Michael Gschwind, Dietmar Maurer {mike,dm} Technische Universitat Wien ¨ Treitlstraße 1–182–2 A–1040 Wien AUSTRIA

This paper discusses the design of a MIPS-I processor kernel using VHDL. The control structure of this processor is distributed, with a small controller in each pipeline stage controlling sequencing of operations and communication with adjacent pipeline stages. Instruction flow management is performed using asynchronous communication signals. Due to its high-level description and distributed control structure, the kernel can easily be extended. Thus, instruction set extension hardware/software co-evaluation can be performed efficiently using rapid prototyping.

Adapting an instruction set to a particular problem is a difficult task, as many unknown problems have to be explored. To achieve overall optimization of program performance, the execution time equation has to be optimized [4]

execution time =

instructions cycles seconds   program instruction cycle

1. Introduction
To optimize processor performance to a particular application, one approach of hardware/software co-design is instruction set extension. To improve performance on any particular problem, many instruction sets have been proposed. While most proposals thoroughly evaluate the impact of proposed instruction set extensions on the software, the impact on hardware design is rarely evaluated. In this work, we present a processor kernel to support hardware/software coevaluation of instruction set extensions. Depending on the proposed instruction set extensions, an implementation may either be too large to be implemented economically, or the extensions may slow down the processor so that any performance effects of an optimized ISA may be lost. To evaluate hardware effects of instruction set extensions, we have designed an extendible RISC processor architecture. By implementing proposed instruction set extensions, hardware aspects of the proposed extensions can be evaluated.

Due to the many factors involved in performance optimization, suggested optimization solutions often minimize only the number of instructions necessary to solve a problem, or at best the number of cycles. However, many of the suggested special purpose instructions are complex. As a result, it may not be possible to clock an extended processor at the same frequency as the original design. This is often neglected by studies, as the processor characteristics can be difficult to predict, and as a full implementation of a processor is often out of scope. Thus, studies most often use software simulators such as SPIM [10] to predict performance. While these instruction set emulators can be used to test software, generate traces and gather statistics, they do not allow to predict the effects of the extended instruction set architecture on the processor design itself. To investigate hardware/software co-evaluation of various instruction set extensions, we have decided to implement an extensible MIPS-I architecture kernel [6]. This kernel gives us the possibility to study the effects of extended instruction set architectures on processor speed and implementation area. For the processor to be useful for these purposes, we identified the following requirements: high-level description The format of the processor description should be easy to understand and modify. modular To add new instructions, only the relevant parts

EURO-DAC ’96 with EURO-VHDL ’96
0-89791-848-7/96 $4.00 © 1996 IEEE

should have to be modified. A monolithic design would make experiments difficult. extendible All data structures and interfaces should be designed such that new fields can be added with ease. synthesizable The processor description should be synthesizable to derive actual hardware implementations. This work is organized as follows: we discuss the implementation of the MIPS-I processor in...
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