Am2901A Microprocessor Project Report

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AM2901A Microprocessor Project Report
ELEC ENG 3017
5 June 2009

Group Number: Eight (8)

Group Members: Bolei Deng Cen Xing Hong Ker Meng Xu 1158969 1149760 1153446 1149780 1

Executive Summary
The following report discussed the approach undertaken to implement the AM2901A microprocessor slice on a Spartan II FPGA board. It will also highlight the functionality and implementation of the individual modules required for the implementation of the microprocessor. The design includes the implementation details of the required modules and the interconnections between them. The report also discusses an important aspect of the implementation of the microprocessor which is the simulation and testing of the individual modules that have to be adhered to ensure correct operation of the overall microprocessor. Simulation tools available in Xilinx 9.1i will be used to simulate the design that our team has derived. Upon discussion of these sections, this document will provide helpful information that will benefit anyone considering undertaking a similar project.

Table of Contents
1. Introduction ........................................................................................................................................ 1 2. Project Approach ................................................................................................................................ 1 3. Random Access Memory (RAM) ......................................................................................................... 1 3.1 Functionality of the RAM .............................................................................................................. 1 3.2 Design and Implementation .......................................................................................................... 2 3.3 Simulation and Testing.................................................................................................................. 2 3.4 Synthesis........................................................................................................................................ 4 4. Q-register ............................................................................................................................................ 4 4.1 Functionality of the Q-register ...................................................................................................... 4 4.2 Design and Implementation .......................................................................................................... 4 4.3 Simulation and Testing.................................................................................................................. 5 4.3.1 Non-shifting............................................................................................................................ 5 4.3.2 Shifting Up .............................................................................................................................. 5 4.3.3 Shifting Down ......................................................................................................................... 5 4.4 Synthesis........................................................................................................................................ 6 5. RAM/Q-register Shifter ....................................................................................................................... 6 5.1 Functionality of the RAM/Q-register Shifter ................................................................................. 6 5.2 Design and Implementation .......................................................................................................... 6 5.3 Simulation and Testing.................................................................................................................. 7 5.4 Synthesis...........................................................................................................................................
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