Adc Case Study Analysis

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  • Topic: Analog-to-digital converter, Digital, Digital signal processing
  • Pages : 5 (1699 words )
  • Download(s) : 92
  • Published : April 2, 2013
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Design
ADC & DAC
Within the system there are combinations of analogue and digital variables within the system. The purpose of the ADC is to convert analogue signals into digital ones within the system before it can be manipulated by the FPGA. The ADC takes the analogue information provided by the PGA and converts it into digital to be multiplied with the blood flow simulation signal by the FPGA. In order for the ADC input and output to communicate between the PGA and FPGA effectively important factors are 12 bits of accuracy and parallel interface in order to achieve system accuracy and highest resolution possible. The purpose of the DAC is to convert digital signals into analogue ones within the system before it can be transmitted from the system to the ultrasound machine being calibrated. The DAC will interface the digital signal provided by the FPGA and output the analogue representation the system to the output buffer. In order for the DAC to communicate between the FPGA and output buffer effectively important variables of the DAC are 12 bits of accuracy and differential/single in order to achieve system accuracy and highest resolution possible. The ADC requirements are as follows:

* Fully differential or single ended input
* Parallel interface/design
* 12 bit resolution
* 40 MHz sampling rate
* Representation in Two’s compliment
The DAC requirements are as follows:
* Differential or single ended output
* 12 bit resolution
* 40 MHz sampling rate
The input for the ADC is essential for interfacing with the PGA. The output of the PGA will be differential ended which requires the ADC to have a differential ended input. The ADC will benefit being incorporated with a differential input offering advantages ranging from good common mode rejection and reduction in distortion. The control interface for the ADC is in parallel. Parallel interfacing allows for faster routing between the ADC and the PGA and FPGA since they are both in parallel. The benefits of the ADC being in parallel are the noise free transfer of the 12 bits of data to the FPGA to be manipulated and implementation between boards straightforward. Due to high ADC data rate, parallel design processes information more efficiently. Parallel design reduces when the signals from PGA and ADC are multiplied together. The system is required to have an accuracy of 12 bits of accuracy which is part of the project specification and required to insure maximum non linearity which is errors caused by physical imperfections and minimum quantization error which is the dissimilarity between the analogue and the digital signal which is due to the resolution of the digital signal. Since the ADC is 12 bits of accuracy the ADC can hold values from 0 to 2048, meaning the lowest value can be 0 and the highest value can be 2048. The system requires a 40 MHz sampling rate and each sample is stored on a 12 bit variable. Therefore the transmission rate of the ADC is 120000 Kbps. Since the frequency being sent to the ADC is a 12 bit digital input, the ADC needs to 12 bits of accuracy in order to process this data and convert it effectively. The ADC is required to have 12 bits of accuracy as stated in the project specification that there needs to be 12 bits of accuracy. Since the signal coming in from the PGA is 20 MHz, the ADC is required to have a suitable sampling rate to be used in analogue to digital conversion. If the ADC has a low sampling rate the waveform generated will be very different from the initial analogue signal resulting in low quality. If the ADC has a high sampling rate the generated waveform will be very large and there will be need for storage space to hold the generated data. The ADC selected was based on the Nyquist Theorem to attain the best sampling rate for optimum storage and balance within analogue to digital conversion. The Nyquist Theorem states that the sampling rate on ADC convertors needs to be at least two times...
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