It is a 32-bit microprocessor. It has 32 bit data bus and 32 bit address bus, so it can address up to 232 = 4GB of RAM. Features
-Segmentation and paging
-Large memory system(64Tbytes in virtual mode) Operating modes
-Virtual mode Internal architecture: There are 6 parallel functional units: -The bus unit: The bus interface unit provides a 32-bit data bus, a 32-bit address bus and control signals. 8-bit (byte), 16-bit (word) and 32-bit (double word) data transfers are supported. It has separate pins for its address and data bus lines. This processing unit contains the latches and drivers for the address bus, transceivers for the data bus, and control logic for signaling whether a memory input/output, or interrupt acknowledgement bus cycle is to be performed. -The prefetch unit: The prefetch unit performs a mechanism known as an instruction stream queue. This queue permits a prefetch up to 16 bytes (8 memory words) of instruction code which is used by the instruction decoder. Whenever bytes are loaded into the queue they are automatically shifted up through the FIFO to the empty location near the output. -The decode unit: It reads the machine-code instructions from the output side of the prefetch queue and decodes them into microcode instruction format. The instruction queue, a part of the decode unit permits three fully decoded instructions to be held waiting for use by the execution unit. -The execution unit: The execution unit involves the arithmetic/logic unit-ALU, registers, special multiply, divide, and shift hardware, and a control ROM. The control ROM contains the microcode sequences. The execution unit reads the decoded instructions from the instruction queue and performs the operations that are specified. During the execution of an instruction, it requests the segment and page units to generate operand addresses and the bus interface unit to perform read or write bus cycles to access data in memory or I/O devices.
-The segment unit: It produces a translated linear address which the paging unit translates into the physical address. The instructions requiring memory reference send their request to the segmentation unit for logical unit computation and translation and segment protection violation checking.
-The page unit: It translates the linear address generated by prefetch unit to physical address before the prefetch bus cycle request is send to the bus interface unit. It also checks for paging violation. Pin structure of 80386 MICROPROCESSOR: 80386DX microprocessor is a 132-pin pin grid array. The functions of the 80386 pins are as follows: 1) A31-A2: These are the Address Bus connections used to address any of the 1G*32 memory locations found in the memory system. 2) D31-D0: These are the data bus connections used for the transfer of data between the microprocessor and its memory and the I/O systems.
3): These are the Bank Enable signals used to access a byte, word or a double word data from any of the 4 memory banks. These signals are generated internally by the microprocessor with the help of the least two significant lines of the address bus i.e. A1 and A0. 4) M/: This is a memory or IO status signal. When this is 1, a memory device is selected for memory operation and when it is 0, an IO device is selected for IO operation. 5) W/ : This is write/read control signal. When it is 0, it indicates that the read operation is to be performed and when it is 1, it indicates that write operation is to be performed. 6) : This is the...
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