1. Introduction

In this project, a 4 -bit ripple carry adder is designed by using dynamic Manchester carry chain. This adder should be designed in Cadence Virtuoso for both schematics and layout. This adder has 9 inputs, A0~A3, B0~B3 and CLK. When the design is finished, it should be checked in HSPICE for the functionality correctness. The worst case delay in this adder should be found by HSPICE as well.

2. Design

The figure shown below is the schema tics of dynamic carry chain.

Figure 1 Manchester Carry Chain

.

A

B

������������

S

������������

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Table 1 Full Adder Truth Table

From the truth table of full adder, the functions of P and G are easily to get P =A ⊕ B

G =AB

The formula below shows the sum bit.

S (G, P) = ( A ⊕ B) ⊕ ������������ S (G, P) = P ⊕ ������������

3. Schematics

From the schematics and formula shows above, an Inverter, AND gate and XOR gate should be designed to finish the 4 -bit ripple carry adder using Manchester carry chain.

Inverter

An inverter uses one NMOS transistor a nd one PMOS to implement. The figure below shows schematics of inverter.

Figure 2 Inverter

AND Gate

An NAND gate and an Inverter can construct a AND gate. An AND gate need 6 transistors in total. In the dynamic manchester carry chain, G is a and gate. The figure below is an AND gate; G = AB.

Figure 3 AND Gate

XOR Gate

In this XOR gate design, transmission gate is used to implement the XOR gate. There are only 6 transistors to implement XOR gate using transmission gate while the CMOS XOR gate needs 12 transistors. The figure below shows the XOR gate.

In

this

transmission

XOR gate,

an

inverter

Figure 4 XOR gate

needed to implement B '. So, 6 transistors need to implement the whole XOR gate. I n this 4-bit adder, sum bit and propagate bit need XOR gate to implement.

4. Layout

In the layout design, the basic NMOS transistor and PMOS transistor were drawn by myself rather than using the library. The W/L of PMOS transistor is two times larger than

W/L of N MOS transistor.

NMOS Transistor

PMOS Transistor

Inverter

AND Gate

The wave below can show that the AND gate is functional correct.

XOR Gate

The wave below can show that the XOR gate is functional correct.

Final 4 -bit Adder Layout

There are 4 bit slices. In my library, there are two cell views called “Final1” and “FinalFirstbit”. The “Final1” cell view is for the first bit, Ci and S0. The other three bits are built by the cell view called “FinalFirstbit”; that means “FinalFirstbit ” cell view can be reused for three times.

5. Worst Case Delay

When A3A2A1A0=0001 and B3B2B1B0=1111, the worst case of delay happened. In this case every bit has carry out bit.

Figure 5 Input A3A2A1A0=0001

CLK

S0

S1

S2

S3

S4

With the cursor provided by scope, we can know the worst case delay is 0.86ns.

6. Conclusion

The Manchester carry chain is a variation of the carry look-ahead adder that uses shared logic to lower the transistor count. This 4 -bit Manchester carry chain adder computes sum bit by P and G. This adder has lower delay and smaller layout area compared with the original a dder.