3bit Adc

Only available on StudyMode
  • Topic: Analog-to-digital converter, Comparator, Logic gate
  • Pages : 7 (1822 words )
  • Download(s) : 30
  • Published : August 26, 2010
Open Document
Text Preview
DURRMANN Antoine
GEAMBLU Clément
4 AE
I- INTRODUCTION ............................................................................................................................. 1 II- COMPARATORS: ........................................................................................................................... 2 1. SIMPLE COMPARATOR .................................................................................................................... 2 2. COMPLEX COMPARATOR ................................................................................................................ 3 III- VOLTAGE DIVIDER: .................................................................................................................. 5 1. WITH NMOS ................................................................................................................................. 5 2. WITH RESISTOR ............................................................................................................................. 6 IV- BUBBLE ERRORS. .................................................................................................................... 7 V- FINAL DESIGN AND TESTS. ....................................................................................................... 12 VI- CONCLUSION.......................................................................................................................... 14 VII- BIBLIOGRAPHY ....................................................................................................................... 14 ADC 3-bits Flash

DURRMANN Antoine – GEAMBLU Clément 1
I- Introduction
We have decided to design an one-step Flash converter. As shown in the schematic below, in this type of ADC the input signal is compared to the 2n nodes of resistors. At the output of the comparators, the sampled input value can be read in thermometer-code. At the beginning of this project, we were novice in circuit designing. Due to the large number of resistors and comparators (2N−1 comparators required), we have chosen to design a 3-bit Flash A/D Converter (7 comparators required).

We were interested in this type of structure, because there is lots of different components to design: Resistors, logic gates, operational amplifier.
In this report, we will deal with all this functions, beginning with the design of a comparator. Next, we will analyze how we can divide a reference voltage in comparison steps. It is required to decode the thermometer code into binary code. And to conclude, we have decided to add a system to remove the bubble errors of this ADC.

ADC 3-bits Flash
DURRMANN Antoine – GEAMBLU Clément 2
II-Comparators:
1. Simple Comparator
We will use the operational amplifiers as comparator. Let us try to build a very simple comparator:
This comparator is very easy to design, but the test results are not satisfactory. We have simulated this circuit with two inputs: a sinus with an offset of 0.5V and a continuous signal Vseuil=0.5V. The results of the test are just above. It is very easy to observe the inefficiency of this comparison system. It is impossible to reach the 0, and the rise time is obviously too long. That is why, we had decided to search an other comparator, which would be more efficient. ADC 3-bits Flash

DURRMANN Antoine – GEAMBLU Clément 3
2. Complex Comparator
We have decided to do an other comparator, more complex. This comparator introduces a setup of rise time with V-bias.
N1 N2 N3 N4
N5 N6
P1 P2 P3 P4 P5
VDD VDD VDD VDD VDD
VIN+ VIN- VOUT
Vbias
V-bias must be included in VTN of transistor and Vdd/2. VTN provide by transistor characteristic and is approximately 0.2V for optimal functioning. For our system, V-bias must be included in 0.2V and 0.5V. We choose V-bias=0.3V. ADC 3-bits Flash

DURRMANN Antoine – GEAMBLU Clément 4
With V-bias=0.2V, we see a long rise time for V-out and impossible to reach the Vdd. This sample is rejected.
With V-bias=0.9V,...
tracking img