# Realization of Logic Functions

**Topics:**Logic gate, CMOS, MOSFET

**Pages:**19 (2628 words)

**Published:**August 6, 2013

CMOS monoﬂops, latches and ﬂipﬂops

Arithmetic circuits

Buﬀer circuits

Electronics – Complex CMOS digital circuits

Prof. M´rta Rencz, Gergely Nagy a

BME DED

October 25, 2011

Realization of logic functions

CMOS monoﬂops, latches and ﬂipﬂops

Arithmetic circuits

Buﬀer circuits

CMOS logic

Pull-up network:

p-type transistors short circuit, if f (X) = 1 open circuit, if f (X) = 0

Pull-down network:

n-type transistors short circuit, if f (X) = 0 open circuit, if f (X) = 1

For example: NOR gate

y = f (X)

Realization of logic functions

CMOS monoﬂops, latches and ﬂipﬂops

Arithmetic circuits

Buﬀer circuits

Complex gates

Complex gates can be realized at transistor level – which is advantageous as the gate delay is smaller for one complex gate than for the series connection of several simple gates realizing the same function. Usually the number of inputs is limited to 4 (the number of transistors in series between the ground and supply is limited). The realized logic function can be any combination of the AND and NOR functions and there is always an inversion at the output: y = (A + B)C y = AB + CD y = (A + B)CD

Realization of logic functions

CMOS monoﬂops, latches and ﬂipﬂops

Arithmetic circuits

Buﬀer circuits

Complex gate design – an example I.

Let’s design the complex gate realizing the logic function y = (A + B)C First the pull-down network (PDN) is created. The OR function is realized by two n-type FETs connected in parallel. The AND function is realized by two n-type FETs connected in series.

Realization of logic functions

CMOS monoﬂops, latches and ﬂipﬂops

Arithmetic circuits

Buﬀer circuits

Complex gate design – an example II.

Next the pull-up network (PUN) is designed with p-type transistors. The PUN has to create a current path between the supply rail and the output for every logic 1 of the logic function. This can be done by creating the dual network of the PDN. In the dual network every series connection is turned into a parallel connection and vica versa.

Realization of logic functions

CMOS monoﬂops, latches and ﬂipﬂops

Arithmetic circuits

Buﬀer circuits

Complex gate design – done an other way

As the p-type transistors conduct when the input is logic 0, the function has to be inverted using the De Morgan laws. In this case: y = C(A + B) = C + A + B = C + AB As it can now be seen, the two methods yield the same results.

Realization of logic functions

CMOS monoﬂops, latches and ﬂipﬂops

Arithmetic circuits

Buﬀer circuits

The sizing of CMOS gates I.

The sizing of digital gates is realitvely easy:

the length of the transistor channels in the inverter is the shortest value allowed by the technology, the width of the channel of the n-type FET is the minimal value (or a little bit larger), the channel width of the p-type is 1.5..2 times that of the n-type (due to the diﬀerences in charge carrier mobilities).

The basic inverter is able to charge a given capacitance during in a given delay time. Along with the input capacitances of the gates connected to the output of the gate, the wires also contribute to the load capacitance that a gate has to drive. These factors determine the fan-out of a CMOS gate. Usually every gate is designed in multiple forms with 2, 4, ... times larger fan-out. In an inverter this means that the transistors have wider channels.

Realization of logic functions

CMOS monoﬂops, latches and ﬂipﬂops

Arithmetic circuits

Buﬀer circuits

The sizing of CMOS gates II.

In case of complex gates, the values of the basic inverter are used as a basis for the calculations. When transistors of the same size are connected in series, their channel lengths add up; in parallel, their channel lengths add up.

This is just an approximation but the MOS channels can be approximated with resistors with a relatively good accuracy. If two n-type MOS FETs...

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