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Acknowledgments
These course notes were originally developed by me for EE476 in Fall 1996 at Washington State University (WSU). The material in these notes has been derived from several sources. These include Dr. Venu Gopinathan's course notes from Columbia University, Dr. David Rich's analog IC design course notes, Prof. Terri Fiez's EE476 course notes, and Prof. Paul Gray's EE240 lecture notes. Their contributions to these notes are gratefully acknowledged. Also a significant amount of the material is based on the Gray and Meyer textbook. Prof. George La Rue at WSU made a monumental effort in cleaning up and formatting the original hand written notes in MS-WORD. I thank him for this effort and for providing me with the formatted notes. This version of the course notes is directly from him and includes his additions and my recent modifications. Karti Mayaram

Lecture Notes for ECE 422 / EE 522

Fall 2012

Karti Mayaram
Oregon State State University

Page 1 EE 422/522

Page 2 EE 422/522

IC Technologies
CMOS Si Bipolar BiCMOS GaAs (E/D MESFET & HFET) InP Heterojunction Bipolar SiGe Bipolar and BiCMOS

Analog Circuit Hierarchy
Device Technology CMOS, bipolar, GaAs MESFET, HBT Basic Circuits Amplifiers Current mirrors Buffers Functional blocks Operational Amplifiers A/D converters, D/A converters Voltage controlled oscillators Mixers Comparators Phase lock loops Voltage references Filters Subsystems Modulators and Demodulators Optical and wireless transceivers DSL and LAN modems Systems Cellular phones Disk and CD ROM drives Modems Measurement instruments Automobile air bag

Applications
Telecommunications Optical Wireless DSL Computing Applications A/Ds and D/As Audio including voice Displays Disk drives and CDROMs Sensors and Actuators Automotive Engine control Displays Anticollision systems Airbags Biomedical Pacemakers Hearing aids Page 3 EE 422/522

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Advantages of single-chip implementation
1) Reduced system size – cell phones, hearing aids. 2) Increased speed – no parasitic capacitances from pins and interconnect 3) Reduced power dissipation – fewer off chip drivers required 4) Increased reliability – fewer packages, fewer interconnects and fewer bond wires (connections are most unreliable) 5) Reduced cost – smaller and simpler printed circuit boards, fewer packages (It costs about $10,000 per kg to launch a satellite)

MOSFET Operation Simplified (Fluid Dynamics Analog) VT = turn-on Voltage (threshold voltage) 1) Cut off: VGS < VT, VDS = 0 S N+ G D N+
Source Tank
VGS

Gate VT

Drain Tank

2) Strong Inversion: VGS > VT, VDS = 0
S N+ G D N+
VGS

Disadvantages
Integrating digital and analog components on same chip may increase design time and number of iterations due to noise coupling Other technologies may offer improved performance For instance, InP low noise amplifiers have lower noise figure than other technologies and may set the performance level for the whole system.

VT

3) Non-saturation: VGS > VT , 0 < VDS < VG - VT
S N+ G D N+
VGS
VDS

VT

4) Saturation: VGS > VT , 0 < VDS > VG - VT Flow becomes independent of VDS S N+
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G

D N+
VGS
VT

VDS

The MOSFET
Enhancement mode n-channel transistor (NMOSFET)
L W
I DS 0 K' W VGS L

Basic MOSFET Equations

N-channel MOSFET Equations (simple model)
VGS VT V DS
2

VT VT , VDS VGS VT

Cut Off Triode Saturation

S N+

G

D N+

I DS

V DS 2

2

1

V DS

VGS

I DS VT K'

1 W K ' VGS 2 L VT 0 C ox

VT

1

V DS
2

VGS
F

VT , VDS

VGS

VT

P-type Substrate (Body) B

VSB C ox

3.45 fF /

2

for t = 10 nm

MOSFET Symbols
N-channel FETs
M1

are process parameters K’, VT0, W and L are device geometry parameters The simplest model in SPICE (Level 1 or default model) uses the above equations. Parameter K’ VT0 SPICE Parameter KP VTO GAMMA LAMBDA PHI Units A/V2 V V0.5 V-1 V

P-channel FETs

M1

M1...
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