Operating System Soluion Manual

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INSTRUCTORS MANUAL

OPERATING SYSTEMS:
INTERNALS AND DESIGN PRINCIPLES
FOURTH EDITION

WILLIAM STALLINGS

Copyright 2000: William Stalling
TABLE OF CONTENTS

PART ONE: SOLUTIONS MANUAL ...............................................................................1 Chapter 1:
Computer System Overview ......................................................................2 Chapter 2:
Operating System Overview ......................................................................6 Chapter 3:
Process Description and Control ...............................................................7 Chapter 4:
Threads, SMP, and Microkernels.............................................................12 Chapter 5:
Concurrency: Mutual Exclusion and Synchronization.........................15 Chapter 6:
Concurrency: Deadlock and Starvation..................................................26 Chapter 7:
Memory Management ...............................................................................34 Chapter 8:
Virtual Memory..........................................................................................38

Part One
SOLUTIONS MANUAL

This manual contains solutions to all of the problems in Operating Systems, Fourth Edition. If you spot an error in a solution or in the wording of a problem, I would greatly appreciate it if you would forward the information via email to me at ws@shore.net. An errata sheet for this manual, if needed, is available at ftp://ftp.shore.net/members/ws/S/ W.S.

-1-

CHAPTER 1
COMPUTER SYSTEM OVERVIEW
ANSWERS TO PROBLEMS
1.1

Memory (contents in hex): 300: 3005; 301: 5940; 302: 7006
Step 1: 3005 → IR; Step 2: 3 → AC
Step 3: 5940 → IR; Step 4: 3 + 2 = 5 → AC
Step 5: 7006 → IR; Step 6: AC → Device 6

1.2

1. a. The PC contains 300, the address of the first instruction. This value is loaded in to the MAR.
b. The value in location 300 (which is the instruction with the value 1940 in hexadecimal) is loaded into the MBR, and the PC is incremented. These two steps can be done in parallel.
c. The value in the MBR is loaded into the IR.
2. a. The address portion of the IR (940) is loaded into the MAR. b. The value in location 940 is loaded into the MBR.
c. The value in the MBR is loaded into the AC.
3. a. The value in the PC (301) is loaded in to the MAR.
b. The value in location 301 (which is the instruction with the value 5941) is loaded into the MBR, and the PC is incremented.
c. The value in the MBR is loaded into the IR.
4. a. The address portion of the IR (941) is loaded into the MAR. b. The value in location 941 is loaded into the MBR.
c. The old value of the AC and the value of location MBR are added and the result is stored in the AC.
5. a. The value in the PC (302) is loaded in to the MAR.
b. The value in location 302 (which is the instruction with the value 2941) is loaded into the MBR, and the PC is incremented.
c. The value in the MBR is loaded into the IR.
6. a. The address portion of the IR (941) is loaded into the MAR. b. The value in the AC is loaded into the MBR.
c. The value in the MBR is stored in location 941.

1.3

a. 224 = 16 MBytes
b. (1) If the local address bus is 32 bits, the whole address can be transferred at once and decoded in memory. However, since the data bus is only 16 bits, it will require 2 cycles to fetch a 32-bit instruction or operand. (2) The 16 bits of the address placed on the address bus can't access the whole memory. Thus a more complex memory interface control is needed to latch the first part of the address and then the second part (since the microprocessor will -2-

end in two steps). For a 32-bit address, one may assume the first half will decode to access a "row" in memory, while the second half is sent later to access a "column" in memory. In addition to the two-step address operation, the microprocessor will need 2 cycles to fetch the 32 bit instruction/operand. c. The program counter must be at least 24...
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