Microprocessor 8086

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3.1 Introduction

This unit explains how to design and implement an 8086 based microcomputer system. To design an 8086 based system, it is necessary to know how to interface the 8086 microprocessor with memory and input and output devices. Due to the mismatch in the speed between the microprocessor and other devices, a set of latches and buffers are required to interface the microprocessor with other devices. In this unit, you will learn about the way in which address/data buses, latches and buffers are used in the process of interfacing. To understand the interfacing principles and concepts it is necessary to learn the various types of bus cycles and bus timings. Overall, this unit makes you to understand how 8086 microprocessor is interfaced with memory and peripherals and how an 8086 based microcomputer system works.

3.2 Learning Objectives

• To study about the operating modes of 8086
• To study about the components of an 8086 based microcomputer system • To understand the address/data buses of an 8086 based system • To understand the necessity of latches and buffers

• To learn the various types of bus cycles
• To learn the bus timings
• To study about the interfacing principles and ideas

3.3 8086-Based Microcomputer System

An 8086-based microcomputer system has the following components. • 8086 CPU
• Peripherals
• Control bus
• Address bus
• Data bus
• Clock generator
• Interrupt Controller
• DMA Controller
• Latches
• Transceivers

The basic control bus consists of the signals labeled M/IO (Active Low), RD (Active Low) and WR (Active Low). If the operation to be performed by 8086 is a read (either from a memory location or from a port) the RD (Active Low) goes low and if the operation to be performed by 8086 is a write (either to a memory location or to a port) the WR (Active Low) signal is asserted. If the read or write operation involves a memory M/IO (Active Low) signal will be high and if the read or write operation involves a port M/IO (Active Low) signal goes low. The other two buses of 8086 are address bus and data bus. These two buses are represented as ADDR/DATA. The logic behind this is to save number of pins. The lower 16 bits of addresses are multiplexed on the data bus.

In any operation where 8086 accesses memory or a port, the 8086 sends out the lower 16 bits of the address on the data bus. External latches such as the 74LS373 octal devices are used to grab this address and hold it during the rest of the operation. To strobe these latches at the proper time, 8086 outputs a signal called Address Latch Enable or ALE. Once the address is stored on the outputs of the latches, the 8086 removes the address from the address/data bus and uses the bus for reading or writing data.

8286 transceiver is used by most of the devices such as ROMs, RAMs and ports. These devices connected on microprocessor buses have MOS inputs and hence they do not require much current. However, each input or output added to the system data bus acts like a capacitor of a few picofarads connected to ground. In order to change the logic state of these signal lines from low to high, all this added capacitance must be charged. To change the logic state to a low, the capacitance must be discharged. If we connect more than a few devices on the data bus lines, the 8086 outputs can not supply enough current drive to charge and discharge the circuit capacitance fast enough. Hence we add external high-current drive buffers to do the job. Buffers used on the data bus must be bidirectional because the 8086 sends data out on the data bus and also reads data in on the data bus. The DT/R (Active Low) from the 8086 sets the direction in which data will pass through the buffers. When DT/R (Active Low) is asserted high, the buffers will be set up to transmit data from the 8086 to ROM, RAM...
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