The eSOC II Board
As mentioned in Lecture 3 and the textbook, most logic circuits today are built using programmable logic devices (PLDs). These devices allow circuits to be built directly onto single chips, without the need for interconnection of separate, single purpose ICs. The eSOC II (electronic System-on-a-Chip) board is designed to allow a direct interface between the Quartus II software and the Altera Cyclone II EP2C8 FPGA. The board provides an interface to the chip, along with supporting interface hardware. Details about the construction and use of the eSOC II board are available in the eSOC II Users Guide supplied with the board. The following is a summary of data taken from that Guide. The eSOC II board is shown in Figure 1 (taken from the User Guide from Arches Computing Systems). The board contains the Altera FPGA (in the center), a 24 MHz clock source (U8 to the left of the FPGA), and numerous input switches and output displays. Figure 1 – eSOC II Board (from User Guide September 6, 2006) There are three types of input switches, single-pole-double-throw (SPDT) toggle switches (S1 and S2), debounced push-button (SPST) switches (DB0 and DB1), and non-debounced push-button switches (B0 – B3). Bouncing is a mechanical effect where a switch rapidly alternates between “on” and “off” when pressed as the metal contacts make and break connection as the parts “bounce” off each other. A debounced switch is designed so that any closure produces a single on to off or off to on indication. The output features include red LEDs (RED0 – RED7), green LEDs (GRN0 – GRN7) and two seven-segment displays (Digit0 and Digit1). The FPGA uses a random access memory (RAM) technology. This will be explained in a later course, for now the key concept is that a program is stored and maintained only as long as the power is applied (like a document you forget to save, the data disappears when the power is removed). This means that every time the eSOC II board is turned off, the...
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