Eece353 Final Exam Summary
UNIVERSITY OF BRITISH COLUMBIA DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EECE 353 – Digital Systems Design Spring 2012 Review for the Final Exam
The final exam will be as advertised in the university examination schedule. The length of the exam is 2.5 hours. You are allowed to bring two single-sided handwritten sheet of notes (no photocopies) to the exam (or one double sided sheet). I actually don’t know what you could put on this sheet that would be useful, but some people find it more comforting to have some notes available. Your sheet must not be typed (even part of it) and you can't photocopy someone else's sheet. You can also bring a calculator. No cell phones, not even as time-pieces. In terms of material, the final will cover everything up to the end of Slide Set 14 (not Slide Set 15). More specifically, we have covered this (this is not a complete list): Slide Set 1: Introduction: not a lot to study here Slide Set 2: Combinational Logic: In this section, we talked about combinational logic, and how to specify combinational logic in VHDL. We talked about structural specifications, packages, libraries, buses, attributes of buses, and std_logic vs. bit. In previous years, we talked about the “with” and “when” statement, however I didn’t discuss that this year, because they are not that commonly used. Slide Set 3: The Process and Sequential Circuits: In this section, we first talked about how to implement a DFF using a process We then generalized it a bit to talk about state machines. We also talked about asynchronous vs. synchronous resets. Then we talked about how to implement combinational logic using a process. Slide Set 4: In Slide Set 4, the focus was on how to write Synthesizable VHDL. Remember, the underlying rule is that each process in your design has to fall into one of the three categories I described: purely combinational, purely sequential, and sequential with an asynchronous set and reset. Surely, on the exam, you will be asked to write
The final exam will be as advertised in the university examination schedule. The length of the exam is 2.5 hours. You are allowed to bring two single-sided handwritten sheet of notes (no photocopies) to the exam (or one double sided sheet). I actually don’t know what you could put on this sheet that would be useful, but some people find it more comforting to have some notes available. Your sheet must not be typed (even part of it) and you can't photocopy someone else's sheet. You can also bring a calculator. No cell phones, not even as time-pieces. In terms of material, the final will cover everything up to the end of Slide Set 14 (not Slide Set 15). More specifically, we have covered this (this is not a complete list): Slide Set 1: Introduction: not a lot to study here Slide Set 2: Combinational Logic: In this section, we talked about combinational logic, and how to specify combinational logic in VHDL. We talked about structural specifications, packages, libraries, buses, attributes of buses, and std_logic vs. bit. In previous years, we talked about the “with” and “when” statement, however I didn’t discuss that this year, because they are not that commonly used. Slide Set 3: The Process and Sequential Circuits: In this section, we first talked about how to implement a DFF using a process We then generalized it a bit to talk about state machines. We also talked about asynchronous vs. synchronous resets. Then we talked about how to implement combinational logic using a process. Slide Set 4: In Slide Set 4, the focus was on how to write Synthesizable VHDL. Remember, the underlying rule is that each process in your design has to fall into one of the three categories I described: purely combinational, purely sequential, and sequential with an asynchronous set and reset. Surely, on the exam, you will be asked to write