A Tutorial

IEEE Dallas CAS Workshop 2000 Edgar Sánchez-Sinencio

March 27, 2000

http://amsc.tamu.edu/

Texas A&M University

Analog and Mixed-Signal Center

Low Voltage Analog Circuit Design Techniques: Roadmap

Low voltage (LV) power supply circuit design techniques are addressed in this tutorial. In particular: (i) Introduction; (ii) Transistor models capable to provide performance and power consumption tradeoffs; (iii) Low voltage implementation techniques, such as floating gates and bulk driven; (iv) Basic building blocks not involving cascode structures, and (v) LV circuit implementations examples. Analog and Mixed-Signal Center, TAMU

Motivation

The need for analog circuits in modern mixed-signal VLSI chips for multimedia, perception, control, instrumentation medical electronics and telecommunication is very high. • What are the challenges in designing low voltage circuits ? - To operate with power supplies smaller than 3.3 volts - To design circuits with the same performance or better than circuits designed for larger power supplies - To perform with technologies smaller than 0.5 micron -To come with new design alternatives, Analog and Mixed-Signal Center, TAMU

( continues)

• Why are we concerned in designing low voltage circuits ? - Designers can not use conventional cascode structures, and other conventional design methodologies. - Circuits should have the same performance or better than circuits designed for larger power supplies - Circuit performance with technologies smaller than 0.5um must be better than circuits for larger technologies. -Third-generation communication applications require circuits ( and systems) with improved dynamic range over a much wider bandwidth. - New building blocks and system must be designed to satisfy the needs of portable, lighter and faster equipment Analog and Mixed-Signal Center, TAMU

Issues about low power supply voltage

Scaling down size technology and supply voltage does not scale linearly the “ VTH hat ”

VTH

VTH

Mister 5 volts IC

Mister 0.8 volts IC

• Threshold and VDSAT do not scale down linearly with power supply nor with smaller size technologies. • Let us consider an illustrative example of a cascode and a simple inverting amplifiers, assume transistors MC and MS carry the same current IL, VT= 0.75V and VDS(SAT)=0.2V • Keeping the same output voltage swing for both circuits

involve the tradeoffs shown in the plot of transistor sizes and GBW vs. Power Supply Voltage

• How to determine how much bias current is needed for certain application ?

• When a designer operates transistors in saturation, what does it mean VDS > VDS(SAT) ? • Can a circuit have their transistors operating in the transition region ? What transistor model equation can be employed ?

One Equation-All Regions Transistor Model

• Features of ACM model: – physics-based model, – universal and continuous expression for any inversion, – independent of technology, temperature, geometry and gate voltage, – same model for analysis, characterization and design. • Main design equations: (design parameters: I, gm, if) f

I t g m n

=

1

+

1 2

+

if

fT =

mf t

2pL2

2( 1 + i f − 1)

W gm 1 = L mCoxft 1 + i f − 1

VDSAT

ft ≅

I drain current in transistor gm transconductance in saturation n slope factor ft thermal voltage if inversion level of the transistor defined as , where I = mnC f W if = I I s 2 L is the normalization current. 2 t s ox

(

1 + i f − 1) + 4

if > 1

weak inversion, strong inversion.

W = L

gm 2 mC oxft

I − 1 ft g m n

Normalized Current

if

=

Transconductance-to-Current Ratio

φ t ng m

ID IS

2 ft

ID

W 2 L

φ tgm

0 I D 10

=

2 1 + 1 + id

IS

′ = m n Cox

ID: saturation current IS: normalization current n: slope factor 10

-1

( (

) theory (n=1.35) ) simulation

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